Lines Matching +full:0 +full:xac00
25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
64 #define IQS7222_COMMS_ERROR 0xEEEE
85 #define IQS7222_REG_OFFSET 0x100
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
327 .base = 0x8000,
332 .base = 0x8700,
337 .base = 0x9000,
342 .base = 0xA000,
347 .base = 0xAC00,
353 .base = 0xB000,
358 .base = 0xC000,
387 .base = 0x8000,
392 .base = 0x8700,
397 .base = 0x9000,
402 .base = 0xA000,
407 .base = 0xAC00,
413 .base = 0xB000,
418 .base = 0xC000,
442 .base = 0x8000,
447 .base = 0x8A00,
452 .base = 0x9000,
457 .base = 0xB000,
462 .base = 0xC400,
485 .base = 0x8000,
490 .base = 0x8A00,
495 .base = 0x9000,
500 .base = 0xB000,
505 .base = 0xC400,
533 .base = 0x8000,
538 .base = 0x8500,
543 .base = 0x9000,
548 .base = 0xA000,
553 .base = 0xAA00,
559 .base = 0xB000,
564 .base = 0xC000,
591 .base = 0x8000,
596 .base = 0x8500,
601 .base = 0x9000,
606 .base = 0xA000,
611 .base = 0xAA00,
617 .base = 0xB000,
622 .base = 0xC000,
648 .base = 0x8000,
653 .base = 0x8700,
658 .base = 0x9000,
663 .base = 0xA000,
668 .base = 0xAE00,
674 .base = 0xB000,
679 .base = 0xC000,
705 .base = 0x8000,
710 .base = 0x8700,
715 .base = 0x9000,
720 .base = 0xA000,
725 .base = 0xAE00,
731 .base = 0xB000,
736 .base = 0xC000,
749 .fw_major = 0,
762 .base = 0x8000,
767 .base = 0x8700,
772 .base = 0x9000,
777 .base = 0xA000,
782 .base = 0xAE00,
788 .base = 0xB000,
793 .base = 0xC000,
824 .reg_offset = 0,
832 .reg_offset = 0,
833 .reg_shift = 0,
870 .reg_shift = 0,
894 .reg_shift = 0,
901 .reg_offset = 0,
909 .reg_offset = 0,
926 .reg_shift = 0,
934 .reg_shift = 0,
941 .reg_offset = 0,
949 .reg_offset = 0,
956 .reg_offset = 0,
963 .reg_offset = 0,
970 .reg_offset = 0,
977 .reg_offset = 0,
984 .reg_offset = 0,
985 .reg_shift = 0,
1011 .reg_shift = 0,
1036 .reg_shift = 0,
1052 .reg_shift = 0,
1060 .reg_offset = 0,
1069 .reg_offset = 0,
1078 .reg_offset = 0,
1079 .reg_shift = 0,
1089 .reg_shift = 0,
1105 .reg_offset = 0,
1113 .reg_offset = 0,
1121 .reg_offset = 0,
1129 .reg_offset = 0,
1130 .reg_shift = 0,
1146 .reg_shift = 0,
1153 .reg_offset = 0,
1162 .reg_offset = 0,
1170 .reg_offset = 0,
1179 .reg_offset = 0,
1187 .reg_offset = 0,
1204 .reg_shift = 0,
1273 .reg_shift = 0,
1283 .reg_shift = 0,
1291 .reg_offset = 0,
1301 .reg_offset = 0,
1302 .reg_shift = 0,
1320 .reg_shift = 0,
1336 .reg_shift = 0,
1353 .reg_shift = 0,
1382 .reg_shift = 0,
1392 .reg_shift = 0,
1401 .reg_shift = 0,
1408 .reg_offset = 0,
1416 .reg_shift = 0,
1425 .reg_shift = 0,
1433 .reg_shift = 0,
1441 .reg_shift = 0,
1450 .reg_shift = 0,
1458 .reg_shift = 0,
1467 .reg_shift = 0,
1475 .reg_shift = 0,
1550 if (ret < 0) in iqs7222_irq_poll()
1552 else if (ret > 0) in iqs7222_irq_poll()
1553 return 0; in iqs7222_irq_poll()
1554 } while (ktime_compare(ktime_get(), irq_timeout) < 0); in iqs7222_irq_poll()
1565 return 0; in iqs7222_hard_reset()
1570 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); in iqs7222_hard_reset()
1581 u8 msg_buf[] = { 0xFF, }; in iqs7222_force_comms()
1587 * ever all write data is ignored, and all read data returns 0xEE. in iqs7222_force_comms()
1598 if (ret < 0) in iqs7222_force_comms()
1600 else if (ret > 0) in iqs7222_force_comms()
1601 return 0; in iqs7222_force_comms()
1605 if (ret >= 0) in iqs7222_force_comms()
1628 .flags = 0, in iqs7222_read_burst()
1650 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_read_burst()
1652 if (ret < 0) in iqs7222_read_burst()
1657 if (ret >= 0) in iqs7222_read_burst()
1669 ret = 0; in iqs7222_read_burst()
1679 if (ret < 0) in iqs7222_read_burst()
1681 "Failed to read from address 0x%04X: %d\n", reg, ret); in iqs7222_read_burst()
1697 return 0; in iqs7222_read_word()
1729 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_write_burst()
1731 if (ret < 0) in iqs7222_write_burst()
1736 if (ret >= 0) in iqs7222_write_burst()
1743 ret = 0; in iqs7222_write_burst()
1751 if (ret < 0) in iqs7222_write_burst()
1753 "Failed to write to address 0x%04X: %d\n", reg, ret); in iqs7222_write_burst()
1769 u16 sys_status = 0; in iqs7222_ati_trigger()
1783 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { in iqs7222_ati_trigger()
1808 return 0; in iqs7222_ati_trigger()
1827 } while (ktime_compare(ktime_get(), ati_timeout) < 0); in iqs7222_ati_trigger()
1830 "ATI attempt %d of %d failed with status 0x%02X, %s\n", in iqs7222_ati_trigger()
1850 iqs7222->sys_setup[0] | in iqs7222_dev_init()
1877 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_dev_init()
1888 val = iqs7222_setup(iqs7222, i, 0); in iqs7222_dev_init()
1896 for (j = 0; j < num_row; j++) { in iqs7222_dev_init()
1901 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1906 for (k = 0; k < num_col; k++) in iqs7222_dev_init()
1946 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; in iqs7222_dev_init()
1947 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; in iqs7222_dev_init()
1948 return 0; in iqs7222_dev_init()
1966 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { in iqs7222_dev_info()
1967 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) in iqs7222_dev_info()
1979 return 0; in iqs7222_dev_info()
1987 le16_to_cpu(dev_id[0])); in iqs7222_dev_info()
2003 return 0; in iqs7222_gpio_select()
2006 return 0; in iqs7222_gpio_select()
2013 } else if (count < 0) { in iqs7222_gpio_select()
2028 for (i = 0; i < count; i++) { in iqs7222_gpio_select()
2046 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_gpio_select()
2051 return 0; in iqs7222_gpio_select()
2065 return 0; in iqs7222_parse_props()
2067 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { in iqs7222_parse_props()
2119 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
2132 return 0; in iqs7222_parse_props()
2159 return 0; in iqs7222_parse_event()
2168 return 0; in iqs7222_parse_event()
2187 return 0; in iqs7222_parse_event()
2208 return 0; in iqs7222_parse_cycle()
2211 if (count < 0) { in iqs7222_parse_cycle()
2231 for (i = 0; i < count; i++) { in iqs7222_parse_cycle()
2241 return 0; in iqs7222_parse_cycle()
2260 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_chan()
2292 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; in iqs7222_parse_chan()
2317 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2330 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; in iqs7222_parse_chan()
2344 if (count < 0) { in iqs7222_parse_chan()
2366 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); in iqs7222_parse_chan()
2368 for (i = 0; i < count; i++) { in iqs7222_parse_chan()
2369 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; in iqs7222_parse_chan()
2378 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); in iqs7222_parse_chan()
2382 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { in iqs7222_parse_chan()
2424 dev_desc->touch_link - (i ? 0 : 2), in iqs7222_parse_chan()
2463 if (count < 0) { in iqs7222_parse_sldr()
2487 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; in iqs7222_parse_sldr()
2489 sldr_setup[0] |= count; in iqs7222_parse_sldr()
2490 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); in iqs7222_parse_sldr()
2492 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_sldr()
2493 sldr_setup[5 + reg_offset + i] = 0; in iqs7222_parse_sldr()
2576 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); in iqs7222_parse_sldr()
2585 sldr_setup[0] &= ~dev_desc->wheel_enable; in iqs7222_parse_sldr()
2587 sldr_setup[0] |= dev_desc->wheel_enable; in iqs7222_parse_sldr()
2596 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) in iqs7222_parse_sldr()
2599 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { in iqs7222_parse_sldr()
2647 * coordinate field reports 0xFFFF and solely relies on touch in iqs7222_parse_sldr()
2688 if (count < 0) { in iqs7222_parse_tpad()
2707 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0); in iqs7222_parse_tpad()
2709 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { in iqs7222_parse_tpad()
2710 tpad_setup[8 + i] = 0; in iqs7222_parse_tpad()
2732 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) in iqs7222_parse_tpad()
2736 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) { in iqs7222_parse_tpad()
2764 * coordinate fields report 0xFFFF and solely relies on touch in iqs7222_parse_tpad()
2775 if (!iqs7222->tp_code[0]) in iqs7222_parse_tpad()
2776 return 0; in iqs7222_parse_tpad()
2779 0, (tpad_setup[4] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2782 0, (tpad_setup[5] ? : 1) - 1, 0, 0); in iqs7222_parse_tpad()
2795 return 0; in iqs7222_parse_tpad()
2829 return 0; in iqs7222_parse_reg_grp()
2843 return 0; in iqs7222_parse_reg_grp()
2859 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { in iqs7222_parse_all()
2862 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; in iqs7222_parse_all()
2863 gpio_setup[1] = 0; in iqs7222_parse_all()
2864 gpio_setup[2] = 0; in iqs7222_parse_all()
2873 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) in iqs7222_parse_all()
2874 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); in iqs7222_parse_all()
2876 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); in iqs7222_parse_all()
2879 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { in iqs7222_parse_all()
2882 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; in iqs7222_parse_all()
2883 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; in iqs7222_parse_all()
2885 chan_setup[5] = 0; in iqs7222_parse_all()
2888 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_parse_all()
2891 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; in iqs7222_parse_all()
2894 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { in iqs7222_parse_all()
2895 for (j = 0; j < reg_grps[i].num_row; j++) { in iqs7222_parse_all()
2902 return 0; in iqs7222_parse_all()
2919 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { in iqs7222_report()
2924 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { in iqs7222_report()
2929 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) in iqs7222_report()
2930 return 0; in iqs7222_report()
2932 for (i = 0; i < num_chan; i++) { in iqs7222_report()
2935 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) in iqs7222_report()
2938 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { in iqs7222_report()
2959 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { in iqs7222_report()
2964 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) in iqs7222_report()
2971 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], in iqs7222_report()
3001 iqs7222->sl_code[i][j], 0); in iqs7222_report()
3004 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) { in iqs7222_report()
3009 input_report_key(iqs7222->keypad, iqs7222->tp_code[0], in iqs7222_report()
3036 iqs7222->tp_code[j], 0); in iqs7222_report()
3041 return 0; in iqs7222_report()
3124 if (irq < 0) in iqs7222_probe()