3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
16  *      - Redistributions of source code must retain the above
20  *      - Redistributions in binary form must reproduce the above
43  * Originally written for a not-quite-i2c serial eeprom, which is
45  * variety of other uses, most board-specific, so the bit-boffing
46  * part has been split off to this file, while the other parts
47  * have been moved to chip-specific files.
50  * we don't know whether '1' is the higher voltage) interface, as
55 #define READ_CMD 1
59  * i2c_wait_for_writes - wait for a write
74 	dd->f_gpio_mod(dd, 0, 0, 0);  in i2c_wait_for_writes()
93 	udelay(1);  in scl_out()
95 	mask = 1UL << dd->gpio_scl_num;  in scl_out()
97 	/* SCL is meant to be bare-drain, so never set "OUT", just DIR */  in scl_out()
98 	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);  in scl_out()
109 		for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {  in scl_out()
110 			if (mask & dd->f_gpio_mod(dd, 0, 0, 0))  in scl_out()
125 	mask = 1UL << dd->gpio_sda_num;  in sda_out()
127 	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */  in sda_out()
128 	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);  in sda_out()
139 	bnum = dd->gpio_sda_num;  in sda_in()
140 	mask = (1UL << bnum);  in sda_in()
141 	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */  in sda_in()
142 	dd->f_gpio_mod(dd, 0, 0, mask);  in sda_in()
143 	read_val = dd->f_gpio_mod(dd, 0, 0, 0);  in sda_in()
150  * i2c_ackrcv - see if ack following write is true
159 	ack_received = sda_in(dd, 1);  in i2c_ackrcv()
160 	scl_out(dd, 1);  in i2c_ackrcv()
161 	ack_received = sda_in(dd, 1) == 0;  in i2c_ackrcv()
169  * rd_byte - read a byte, sending STOP on last, else ACK
181 	for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {  in rd_byte()
182 		data <<= 1;  in rd_byte()
183 		scl_out(dd, 1);  in rd_byte()
188 		scl_out(dd, 1);  in rd_byte()
192 		scl_out(dd, 1);  in rd_byte()
194 		sda_out(dd, 1);  in rd_byte()
200  * wr_byte - write a byte, one bit at a time
204  * Returns 0 if we got the following ack, otherwise 1
211 	for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {  in wr_byte()
212 		bit = (data >> bit_cntr) & 1;  in wr_byte()
214 		scl_out(dd, 1);  in wr_byte()
217 	return (!i2c_ackrcv(dd)) ? 1 : 0;  in wr_byte()
226 	sda_out(dd, 1);  in start_seq()
227 	scl_out(dd, 1);  in start_seq()
229 	udelay(1);  in start_seq()
234  * stop_seq - transmit the stop sequence
243 	scl_out(dd, 1);  in stop_seq()
244 	sda_out(dd, 1);  in stop_seq()
248  * stop_cmd - transmit the stop condition
260  * qib_twsi_reset - reset I2C communication
268 	u32 pins, mask;  in qib_twsi_reset()  local
273 	mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);  in qib_twsi_reset()
276 	 * Force pins to desired innocuous state.  in qib_twsi_reset()
277 	 * This is the default power-on state with out=0 and dir=0,  in qib_twsi_reset()
278 	 * So tri-stated and should be floating high (barring HW problems)  in qib_twsi_reset()
280 	dd->f_gpio_mod(dd, 0, 0, mask);  in qib_twsi_reset()
287 	 * if SCL drops between them, another vendor's part will  in qib_twsi_reset()
292 	while (clock_cycles_left--) {  in qib_twsi_reset()
294 		scl_out(dd, 1);  in qib_twsi_reset()
305 		pins = dd->f_gpio_mod(dd, 0, 0, 0);  in qib_twsi_reset()
306 		if ((pins & mask) != mask)  in qib_twsi_reset()
307 			qib_dev_err(dd, "GPIO pins not at rest: %d\n",  in qib_twsi_reset()
308 				    pins & mask);  in qib_twsi_reset()
310 		udelay(1); /* Guarantee .6 uSec setup */  in qib_twsi_reset()
312 		udelay(1); /* Guarantee .6 uSec hold */  in qib_twsi_reset()
314 		sda_out(dd, 1);  in qib_twsi_reset()
330 	int ret = 1;  in qib_twsi_wr()
342 /* Added functionality for IBA7220-based cards */
350  * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
353  * this driver, the device is followed by a one-byte "address" which selects
363 	ret = 1;  in qib_twsi_blk_rd()
366 		/* legacy not-really-I2C */  in qib_twsi_blk_rd()
367 		addr = (addr << 1) | READ_CMD;  in qib_twsi_blk_rd()
374 			ret = 1;  in qib_twsi_blk_rd()
379 		 * but simply issue a start with the "read" dev-addr.  in qib_twsi_blk_rd()
391 			ret = 1;  in qib_twsi_blk_rd()
398 		ret = 1;  in qib_twsi_blk_rd()
409 	while (len-- > 0) {  in qib_twsi_blk_rd()
428  * QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
431  * this driver, the device is followed by a one-byte "address" which selects
441 	int ret = 1;  in qib_twsi_blk_wr()
445 			if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,  in qib_twsi_blk_wr()
464 		len -= sub_len;  in qib_twsi_blk_wr()
486 			if (!--max_wait_time)  in qib_twsi_blk_wr()
490 		rd_byte(dd, 1);  in qib_twsi_blk_wr()
498 	ret = 1;  in qib_twsi_blk_wr()