3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
16  *      - Redistributions of source code must retain the above
20  *      - Redistributions in binary form must reproduce the above
35 #include <linux/delay.h>
43  * Originally written for a not-quite-i2c serial eeprom, which is
45  * variety of other uses, most board-specific, so the bit-boffing
47  * have been moved to chip-specific files.
51  * the restrictions of the generic i2c interface (e.g. no access from
59  * i2c_wait_for_writes - wait for a write
74 	dd->f_gpio_mod(dd, 0, 0, 0);  in i2c_wait_for_writes()
95 	mask = 1UL << dd->gpio_scl_num;  in scl_out()
97 	/* SCL is meant to be bare-drain, so never set "OUT", just DIR */  in scl_out()
98 	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);  in scl_out()
102 	 * delay for falling edge, sampling on rise.  in scl_out()
109 		for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {  in scl_out()
110 			if (mask & dd->f_gpio_mod(dd, 0, 0, 0))  in scl_out()
125 	mask = 1UL << dd->gpio_sda_num;  in sda_out()
127 	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */  in sda_out()
128 	dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);  in sda_out()
139 	bnum = dd->gpio_sda_num;  in sda_in()
141 	/* SDA is meant to be bare-drain, so never set "OUT", just DIR */  in sda_in()
142 	dd->f_gpio_mod(dd, 0, 0, mask);  in sda_in()
143 	read_val = dd->f_gpio_mod(dd, 0, 0, 0);  in sda_in()
150  * i2c_ackrcv - see if ack following write is true
169  * rd_byte - read a byte, sending STOP on last, else ACK
181 	for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {  in rd_byte()
200  * wr_byte - write a byte, one bit at a time
211 	for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {  in wr_byte()
234  * stop_seq - transmit the stop sequence
248  * stop_cmd - transmit the stop condition
260  * qib_twsi_reset - reset I2C communication
270 	/* Both SCL and SDA should be high. If not, there  in qib_twsi_reset()
273 	mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);  in qib_twsi_reset()
277 	 * This is the default power-on state with out=0 and dir=0,  in qib_twsi_reset()
278 	 * So tri-stated and should be floating high (barring HW problems)  in qib_twsi_reset()
280 	dd->f_gpio_mod(dd, 0, 0, mask);  in qib_twsi_reset()
284 	 * If SDA does not go high at any point, we are wedged.  in qib_twsi_reset()
288 	 * wedge, dropping SDA and keeping it low forever, at the end of  in qib_twsi_reset()
292 	while (clock_cycles_left--) {  in qib_twsi_reset()
295 		/* Note if SDA is high, but keep clocking to sync slave */  in qib_twsi_reset()
305 		pins = dd->f_gpio_mod(dd, 0, 0, 0);  in qib_twsi_reset()
309 		/* Drop SDA to issue START */  in qib_twsi_reset()
313 		/* At this point, SCL is high, SDA low. Raise SDA for STOP */  in qib_twsi_reset()
342 /* Added functionality for IBA7220-based cards */
353  * this driver, the device is followed by a one-byte "address" which selects
366 		/* legacy not-really-I2C */  in qib_twsi_blk_rd()
370 		/* Actual I2C */  in qib_twsi_blk_rd()
379 		 * but simply issue a start with the "read" dev-addr.  in qib_twsi_blk_rd()
382 		 * and cannot rely on the delay built in to the STOP  in qib_twsi_blk_rd()
409 	while (len-- > 0) {  in qib_twsi_blk_rd()
431  * this driver, the device is followed by a one-byte "address" which selects
450 			/* Real I2C */  in qib_twsi_blk_wr()
464 		len -= sub_len;  in qib_twsi_blk_wr()
486 			if (!--max_wait_time)  in qib_twsi_blk_wr()