Lines Matching +full:te +full:- +full:irq +full:- +full:pins

2  * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
54 * This file contains all the chip-specific register information and
55 * access functions for the Intel Intel_IB PCI-Express chip.
59 /* KREG_IDX uses machine-generated #defines */
62 /* Use defines to tie machine-generated names to lower-case names */
115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
237 * DDR when faking DDR negotiations with non-IBTA switches.
239 * a non-zero delta.
297 * qib_read_ureg32 - read 32-bit virtualized per-context register
303 * Returns -1 on errors (not distinguishable from valid contents at
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
312 if (dd->userbase) in qib_read_ureg32()
314 ((char __iomem *)dd->userbase + in qib_read_ureg32()
315 dd->ureg_align * ctxt)); in qib_read_ureg32()
318 (dd->uregbase + in qib_read_ureg32()
319 (char __iomem *)dd->kregbase + in qib_read_ureg32()
320 dd->ureg_align * ctxt)); in qib_read_ureg32()
324 * qib_write_ureg - write 32-bit virtualized per-context register
337 if (dd->userbase) in qib_write_ureg()
339 ((char __iomem *) dd->userbase + in qib_write_ureg()
340 dd->ureg_align * ctxt); in qib_write_ureg()
343 (dd->uregbase + in qib_write_ureg()
344 (char __iomem *) dd->kregbase + in qib_write_ureg()
345 dd->ureg_align * ctxt); in qib_write_ureg()
347 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_ureg()
354 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg32()
355 return -1; in qib_read_kreg32()
356 return readl((u32 __iomem *)&dd->kregbase[regno]); in qib_read_kreg32()
362 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg64()
363 return -1; in qib_read_kreg64()
365 return readq(&dd->kregbase[regno]); in qib_read_kreg64()
371 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_kreg()
372 writeq(value, &dd->kregbase[regno]); in qib_write_kreg()
376 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
392 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT)) in write_6120_creg()
393 writeq(value, &dd->cspec->cregbase[regno]); in write_6120_creg()
398 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_6120_creg()
400 return readq(&dd->cspec->cregbase[regno]); in read_6120_creg()
405 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_6120_creg32()
407 return readl(&dd->cspec->cregbase[regno]); in read_6120_creg32()
414 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
416 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
468 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
538 /* chip-specific hardware errors */
616 /* These are all rcv-related errors which we want to count for stats */
625 /* These are all send-related errors which we want to count for stats */
673 qib_devinfo(dd->pcidev, in qib_6120_txe_recover()
681 if (dd->flags & QIB_BADINTR) in qib_6120_set_intr_state()
684 /* force re-interrupt of any pending interrupts. */ in qib_6120_set_intr_state()
695 * Forcibly update the in-memory pioavail register copies after cleanup
702 * This is in chip-specific code because of all of the register accesses,
713 qib_cancel_sends(dd->pport); in qib_6120_clear_freeze()
716 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_clear_freeze()
719 /* force in-memory update now we are out of freeze */ in qib_6120_clear_freeze()
725 * and cancelling sends. Re-enable error interrupts before possible in qib_6120_clear_freeze()
726 * force of re-interrupt on pending interrupts. in qib_6120_clear_freeze()
730 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_6120_clear_freeze()
735 * qib_handle_6120_hwerrors - display hardware errors.
771 hwerrs &= dd->cspec->hwerrmask; in qib_handle_6120_hwerrors()
778 qib_devinfo(dd->pcidev, in qib_handle_6120_hwerrors()
788 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) { in qib_handle_6120_hwerrors()
816 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_handle_6120_hwerrors()
817 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
823 bitsmsg = dd->cspec->bitsmsgbuf; in qib_handle_6120_hwerrors()
829 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), in qib_handle_6120_hwerrors()
836 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), in qib_handle_6120_hwerrors()
841 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL); in qib_handle_6120_hwerrors()
842 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
850 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED; in qib_handle_6120_hwerrors()
851 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
865 if (isfatal && !dd->diag_client) { in qib_handle_6120_hwerrors()
868 dd->serial); in qib_handle_6120_hwerrors()
873 if (dd->freezemsg) in qib_handle_6120_hwerrors()
874 snprintf(dd->freezemsg, dd->freezelen, in qib_handle_6120_hwerrors()
957 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
962 struct qib_devdata *dd = ppd->dd; in qib_disarm_6120_senderrbufs()
973 dd->piobcnt2k + dd->piobcnt4k); in qib_disarm_6120_senderrbufs()
982 if (linkrecov != dd->cspec->lastlinkrecov) { in chk_6120_linkrecovery()
984 dd->cspec->lastlinkrecov = 0; in chk_6120_linkrecovery()
985 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN); in chk_6120_linkrecovery()
989 dd->cspec->lastlinkrecov = in chk_6120_linkrecovery()
999 struct qib_pportdata *ppd = dd->pport; in handle_6120_errors()
1003 errs &= dd->cspec->errormask; in handle_6120_errors()
1004 msg = dd->cspec->emsgbuf; in handle_6120_errors()
1008 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_6120_errors()
1018 !(ppd->lflags & QIBL_LINKACTIVE)) { in handle_6120_errors()
1029 !(ppd->lflags & QIBL_LINKACTIVE)) { in handle_6120_errors()
1052 qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask); in handle_6120_errors()
1066 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov) in handle_6120_errors()
1084 "Got reset, requires re-init (unload and reload driver)\n"); in handle_6120_errors()
1085 dd->flags &= ~QIB_INITTED; /* needs re-init */ in handle_6120_errors()
1087 *dd->devstatusp |= QIB_STATUS_HWERROR; in handle_6120_errors()
1088 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF; in handle_6120_errors()
1092 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); in handle_6120_errors()
1094 if (ppd->state_wanted & ppd->lflags) in handle_6120_errors()
1095 wake_up_interruptible(&ppd->state_wait); in handle_6120_errors()
1116 * qib_6120_init_hwerrors - enable hardware errors
1137 if (dd->minrev < 2) { in qib_6120_init_hwerrors()
1147 dd->cspec->hwerrmask = val; in qib_6120_init_hwerrors()
1150 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_6120_init_hwerrors()
1156 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_6120_init_hwerrors()
1161 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) | in qib_6120_init_hwerrors()
1167 * on chips that are count-based, rather than trigger-based. There is no
1169 * Only chip-specific because it's all register accesses
1176 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr); in qib_set_6120_armlaunch()
1178 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr); in qib_set_6120_armlaunch()
1179 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_6120_armlaunch()
1183 * Formerly took parameter <which> in pre-shifted,
1184 * pre-merged form with LinkCmd and LinkInitCmd
1191 struct qib_devdata *dd = ppd->dd; in qib_set_ib_6120_lstate()
1196 * If we are told to disable, note that so link-recovery in qib_set_ib_6120_lstate()
1199 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_set_ib_6120_lstate()
1200 ppd->lflags |= QIBL_IB_LINK_DISABLED; in qib_set_ib_6120_lstate()
1201 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_set_ib_6120_lstate()
1206 * link-recovery code attempt to bring us back up. in qib_set_ib_6120_lstate()
1208 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_set_ib_6120_lstate()
1209 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; in qib_set_ib_6120_lstate()
1210 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_set_ib_6120_lstate()
1216 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd); in qib_set_ib_6120_lstate()
1217 /* write to chip to prevent back-to-back writes of control reg */ in qib_set_ib_6120_lstate()
1222 * qib_6120_bringup_serdes - bring up the serdes
1227 struct qib_devdata *dd = ppd->dd; in qib_6120_bringup_serdes()
1231 dd->control &= ~QLOGIC_IB_C_LINKENABLE; in qib_6120_bringup_serdes()
1234 dd->cspec->ibdeltainprog = 1; in qib_6120_bringup_serdes()
1235 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr); in qib_6120_bringup_serdes()
1236 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov); in qib_6120_bringup_serdes()
1247 dd->cspec->lli_thresh = 0xf; in qib_6120_bringup_serdes()
1248 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold); in qib_6120_bringup_serdes()
1257 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen); in qib_6120_bringup_serdes()
1258 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */ in qib_6120_bringup_serdes()
1261 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << in qib_6120_bringup_serdes()
1285 * after PLL is reset, set the per-lane Resets and TxIdle and in qib_6120_bringup_serdes()
1320 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) { in qib_6120_bringup_serdes()
1323 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv); in qib_6120_bringup_serdes()
1330 /* clear current and de-emphasis bits */ in qib_6120_bringup_serdes()
1334 /* set de-emphasis to -5.68dB */ in qib_6120_bringup_serdes()
1339 ppd->guid = dd->base_guid; in qib_6120_bringup_serdes()
1342 * the process of setting and un-resetting the serdes normally in qib_6120_bringup_serdes()
1353 dd->control |= QLOGIC_IB_C_LINKENABLE; in qib_6120_bringup_serdes()
1354 dd->control &= ~QLOGIC_IB_C_FREEZEMODE; in qib_6120_bringup_serdes()
1355 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_bringup_serdes()
1361 * qib_6120_quiet_serdes - set serdes to txidle
1367 struct qib_devdata *dd = ppd->dd; in qib_6120_quiet_serdes()
1373 dd->control &= ~QLOGIC_IB_C_LINKENABLE; in qib_6120_quiet_serdes()
1375 dd->control | QLOGIC_IB_C_FREEZEMODE); in qib_6120_quiet_serdes()
1377 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta || in qib_6120_quiet_serdes()
1378 dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1386 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1388 if (dd->cspec->ibdeltainprog) in qib_6120_quiet_serdes()
1389 val -= val - dd->cspec->ibsymsnap; in qib_6120_quiet_serdes()
1390 val -= dd->cspec->ibsymdelta; in qib_6120_quiet_serdes()
1393 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1395 if (dd->cspec->ibdeltainprog) in qib_6120_quiet_serdes()
1396 val -= val - dd->cspec->iblnkerrsnap; in qib_6120_quiet_serdes()
1397 val -= dd->cspec->iblnkerrdelta; in qib_6120_quiet_serdes()
1411 * qib_6120_setup_setextled - set the state of the two external LEDs
1427 * require waking up every 10-20 msecs and checking the counters
1436 struct qib_devdata *dd = ppd->dd; in qib_6120_setup_setextled()
1442 if (dd->diag_client) in qib_6120_setup_setextled()
1446 if (ppd->led_override) { in qib_6120_setup_setextled()
1447 ltst = (ppd->led_override & QIB_LED_PHYS) ? in qib_6120_setup_setextled()
1449 lst = (ppd->led_override & QIB_LED_LOG) ? in qib_6120_setup_setextled()
1460 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_6120_setup_setextled()
1461 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) | in qib_6120_setup_setextled()
1468 dd->cspec->extctrl = extctl; in qib_6120_setup_setextled()
1470 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_6120_setup_setextled()
1474 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1482 kfree(dd->cspec->cntrs); in qib_6120_setup_cleanup()
1483 kfree(dd->cspec->portcntrs); in qib_6120_setup_cleanup()
1484 if (dd->cspec->dummy_hdrq) { in qib_6120_setup_cleanup()
1485 dma_free_coherent(&dd->pcidev->dev, in qib_6120_setup_cleanup()
1486 ALIGN(dd->rcvhdrcnt * in qib_6120_setup_cleanup()
1487 dd->rcvhdrentsize * in qib_6120_setup_cleanup()
1489 dd->cspec->dummy_hdrq, in qib_6120_setup_cleanup()
1490 dd->cspec->dummy_hdrq_phys); in qib_6120_setup_cleanup()
1491 dd->cspec->dummy_hdrq = NULL; in qib_6120_setup_cleanup()
1499 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_wantpiobuf_6120_intr()
1501 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail); in qib_wantpiobuf_6120_intr()
1503 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail); in qib_wantpiobuf_6120_intr()
1504 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in qib_wantpiobuf_6120_intr()
1506 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_wantpiobuf_6120_intr()
1525 qib_devinfo(dd->pcidev, in unlikely_6120_intr()
1540 /* First the error-counter case. */ in unlikely_6120_intr()
1550 dd->cspec->rxfc_unsupvl_errs++; in unlikely_6120_intr()
1552 dd->cspec->overrun_thresh_errs++; in unlikely_6120_intr()
1554 dd->cspec->lli_errs++; in unlikely_6120_intr()
1573 dd->cspec->gpio_mask &= ~(gpiostatus & mask); in unlikely_6120_intr()
1575 dd->cspec->gpio_mask); in unlikely_6120_intr()
1583 static irqreturn_t qib_6120intr(int irq, void *data) in qib_6120intr() argument
1590 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { in qib_6120intr()
1607 if (unlikely(istat == -1)) { in qib_6120intr()
1614 this_cpu_inc(*dd->int_counter); in qib_6120intr()
1623 * the queue, and will re-interrupt if necessary. The processor in qib_6120intr()
1639 for (i = 0; i < dd->first_user_ctxt; i++) { in qib_6120intr()
1642 crcs += qib_kreceive(dd->rcd[i], in qib_6120intr()
1643 &dd->cspec->lli_counter, in qib_6120intr()
1649 u32 cntr = dd->cspec->lli_counter; in qib_6120intr()
1653 if (cntr > dd->cspec->lli_thresh) { in qib_6120intr()
1654 dd->cspec->lli_counter = 0; in qib_6120intr()
1655 dd->cspec->lli_errs++; in qib_6120intr()
1657 dd->cspec->lli_counter += cntr; in qib_6120intr()
1670 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) in qib_6120intr()
1679 * Set up our chip-specific interrupt handler
1688 * If the chip supports added error indication via GPIO pins, in qib_setup_6120_interrupt()
1693 if (SYM_FIELD(dd->revision, Revision_R, in qib_setup_6120_interrupt()
1695 /* Rev2+ reports extra errors via internal GPIO pins */ in qib_setup_6120_interrupt()
1696 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK; in qib_setup_6120_interrupt()
1697 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_6120_interrupt()
1700 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd, in qib_setup_6120_interrupt()
1704 "Couldn't setup interrupt (irq=%d): %d\n", in qib_setup_6120_interrupt()
1705 pci_irq_vector(dd->pcidev, 0), ret); in qib_setup_6120_interrupt()
1709 * pe_boardname - fill in the board name
1718 boardid = SYM_FIELD(dd->revision, Revision, in pe_boardname()
1723 dd->boardname = "InfiniPath_QLE7140"; in pe_boardname()
1727 dd->boardname = "Unknown_InfiniPath_6120"; in pe_boardname()
1731 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2) in pe_boardname()
1734 dd->majrev, dd->minrev); in pe_boardname()
1736 snprintf(dd->boardversion, sizeof(dd->boardversion), in pe_boardname()
1738 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, in pe_boardname()
1739 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), in pe_boardname()
1740 dd->majrev, dd->minrev, in pe_boardname()
1741 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); in pe_boardname()
1760 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); in qib_6120_setup_reset()
1762 /* no interrupts till re-initted */ in qib_6120_setup_reset()
1765 dd->cspec->ibdeltainprog = 0; in qib_6120_setup_reset()
1766 dd->cspec->ibsymdelta = 0; in qib_6120_setup_reset()
1767 dd->cspec->iblnkerrdelta = 0; in qib_6120_setup_reset()
1774 dd->flags &= ~(QIB_INITTED | QIB_PRESENT); in qib_6120_setup_reset()
1776 dd->z_int_counter = qib_int_counter(dd); in qib_6120_setup_reset()
1777 val = dd->control | QLOGIC_IB_C_RESET; in qib_6120_setup_reset()
1778 writeq(val, &dd->kregbase[kr_control]); in qib_6120_setup_reset()
1779 mb(); /* prevent compiler re-ordering around actual reset */ in qib_6120_setup_reset()
1795 val = readq(&dd->kregbase[kr_revision]); in qib_6120_setup_reset()
1796 if (val == dd->revision) { in qib_6120_setup_reset()
1797 dd->flags |= QIB_PRESENT; /* it's back */ in qib_6120_setup_reset()
1806 if (qib_pcie_params(dd, dd->lbus_width, NULL)) in qib_6120_setup_reset()
1812 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_6120_setup_reset()
1820 * qib_6120_put_tid - write a TID in chip
1839 if (!dd->kregbase) in qib_6120_put_tid()
1842 if (pa != dd->tidinvalid) { in qib_6120_put_tid()
1843 if (pa & ((1U << 11) - 1)) { in qib_6120_put_tid()
1857 pa |= dd->tidtemplate; in qib_6120_put_tid()
1875 tidx = tidptr - dd->egrtidbase; in qib_6120_put_tid()
1877 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt) in qib_6120_put_tid()
1878 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock; in qib_6120_put_tid()
1887 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1896 * revision-agnostic form, as they are not performance critical.
1903 if (!dd->kregbase) in qib_6120_put_tid_2()
1906 if (pa != dd->tidinvalid) { in qib_6120_put_tid_2()
1907 if (pa & ((1U << 11) - 1)) { in qib_6120_put_tid_2()
1921 pa |= dd->tidtemplate; in qib_6120_put_tid_2()
1930 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1947 if (!dd->kregbase || !rcd) in qib_6120_clear_tids()
1950 ctxt = rcd->ctxt; in qib_6120_clear_tids()
1952 tidinv = dd->tidinvalid; in qib_6120_clear_tids()
1954 ((char __iomem *)(dd->kregbase) + in qib_6120_clear_tids()
1955 dd->rcvtidbase + in qib_6120_clear_tids()
1956 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_6120_clear_tids()
1958 for (i = 0; i < dd->rcvtidcnt; i++) in qib_6120_clear_tids()
1960 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, in qib_6120_clear_tids()
1964 ((char __iomem *)(dd->kregbase) + in qib_6120_clear_tids()
1965 dd->rcvegrbase + in qib_6120_clear_tids()
1966 rcd->rcvegr_tid_base * sizeof(*tidbase)); in qib_6120_clear_tids()
1968 for (i = 0; i < rcd->rcvegrcnt; i++) in qib_6120_clear_tids()
1970 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, in qib_6120_clear_tids()
1975 * qib_6120_tidtemplate - setup constants for TID updates
1982 u32 egrsize = dd->rcvegrbufsize; in qib_6120_tidtemplate()
1994 dd->tidtemplate = 1U << 29; in qib_6120_tidtemplate()
1996 dd->tidtemplate = 2U << 29; in qib_6120_tidtemplate()
1997 dd->tidinvalid = 0; in qib_6120_tidtemplate()
2006 * qib_6120_get_base_info - set chip-specific flags for user code
2017 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER; in qib_6120_get_base_info()
2019 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE | in qib_6120_get_base_info()
2034 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt); in qib_6120_config_ctxts()
2036 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports; in qib_6120_config_ctxts()
2037 if (dd->first_user_ctxt > dd->ctxtcnt) in qib_6120_config_ctxts()
2038 dd->first_user_ctxt = dd->ctxtcnt; in qib_6120_config_ctxts()
2039 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6; in qib_6120_config_ctxts()
2041 dd->first_user_ctxt = dd->num_pports; in qib_6120_config_ctxts()
2042 dd->n_krcv_queues = dd->first_user_ctxt; in qib_6120_config_ctxts()
2049 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_6120_usrhead()
2050 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_6120_usrhead()
2057 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_6120_hdrqempty()
2058 if (rcd->rcvhdrtail_kvaddr) in qib_6120_hdrqempty()
2061 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_6120_hdrqempty()
2072 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev, in alloc_dummy_hdrq()
2073 dd->rcd[0]->rcvhdrq_size, in alloc_dummy_hdrq()
2074 &dd->cspec->dummy_hdrq_phys, in alloc_dummy_hdrq()
2076 if (!dd->cspec->dummy_hdrq) { in alloc_dummy_hdrq()
2077 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n"); in alloc_dummy_hdrq()
2079 dd->cspec->dummy_hdrq_phys = 0UL; in alloc_dummy_hdrq()
2084 * Modify the RCVCTRL register in chip-specific way. This
2086 * location is chip-specific, but the needed operations are
2087 * generic. <op> is a bit-mask because we often want to
2093 struct qib_devdata *dd = ppd->dd; in rcvctrl_6120_mod()
2097 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_6120_mod()
2100 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); in rcvctrl_6120_mod()
2102 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); in rcvctrl_6120_mod()
2104 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT); in rcvctrl_6120_mod()
2106 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT); in rcvctrl_6120_mod()
2108 mask = (1ULL << dd->ctxtcnt) - 1; in rcvctrl_6120_mod()
2113 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable)); in rcvctrl_6120_mod()
2114 if (!(dd->flags & QIB_NODMA_RTAIL)) in rcvctrl_6120_mod()
2115 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT; in rcvctrl_6120_mod()
2118 dd->rcd[ctxt]->rcvhdrqtailaddr_phys); in rcvctrl_6120_mod()
2120 dd->rcd[ctxt]->rcvhdrq_phys); in rcvctrl_6120_mod()
2122 if (ctxt == 0 && !dd->cspec->dummy_hdrq) in rcvctrl_6120_mod()
2126 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable)); in rcvctrl_6120_mod()
2128 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); in rcvctrl_6120_mod()
2130 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); in rcvctrl_6120_mod()
2131 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in rcvctrl_6120_mod()
2132 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) { in rcvctrl_6120_mod()
2135 dd->rhdrhead_intr_off; in rcvctrl_6120_mod()
2149 dd->rcd[ctxt]->head = val; in rcvctrl_6120_mod()
2151 if (ctxt < dd->first_user_ctxt) in rcvctrl_6120_mod()
2152 val |= dd->rhdrhead_intr_off; in rcvctrl_6120_mod()
2167 dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2169 dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2173 for (i = 0; i < dd->cfgctxts; i++) { in rcvctrl_6120_mod()
2175 i, dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2177 i, dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2181 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_6120_mod()
2185 * Modify the SENDCTRL register in chip-specific way. This
2189 * Chip requires no back-back sendctrl writes, so write
2194 struct qib_devdata *dd = ppd->dd; in sendctrl_6120_mod()
2198 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_6120_mod()
2202 dd->sendctrl = 0; in sendctrl_6120_mod()
2204 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable); in sendctrl_6120_mod()
2206 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable); in sendctrl_6120_mod()
2208 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd); in sendctrl_6120_mod()
2210 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd); in sendctrl_6120_mod()
2215 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_6120_mod()
2220 last = dd->piobcnt2k + dd->piobcnt4k; in sendctrl_6120_mod()
2231 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_6120_mod()
2246 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in sendctrl_6120_mod()
2250 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_6120_mod()
2257 * to occur, so in-memory copy is in sync with in sendctrl_6120_mod()
2269 * qib_portcntr_6120 - read a per-port counter
2276 struct qib_devdata *dd = ppd->dd; in qib_portcntr_6120()
2317 qib_devinfo(ppd->dd->pcidev, in qib_portcntr_6120()
2325 ret = dd->cspec->lli_errs; in qib_portcntr_6120()
2327 ret = dd->cspec->overrun_thresh_errs; in qib_portcntr_6120()
2332 for (i = 0; i < dd->first_user_ctxt; i++) in qib_portcntr_6120()
2335 ret = dd->cspec->pma_sample_status; in qib_portcntr_6120()
2349 if (dd->cspec->ibdeltainprog) in qib_portcntr_6120()
2350 ret -= ret - dd->cspec->ibsymsnap; in qib_portcntr_6120()
2351 ret -= dd->cspec->ibsymdelta; in qib_portcntr_6120()
2353 if (dd->cspec->ibdeltainprog) in qib_portcntr_6120()
2354 ret -= ret - dd->cspec->iblnkerrsnap; in qib_portcntr_6120()
2355 ret -= dd->cspec->iblnkerrdelta; in qib_portcntr_6120()
2358 ret += dd->cspec->rxfc_unsupvl_errs; in qib_portcntr_6120()
2365 * Device counter names (not port-specific), one line per stat,
2370 * Non-error counters are first.
2401 * same as cntr6120names and cntr6120indices, but for port-specific counters.
2476 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts; in init_6120_cntrnames()
2485 dd->cspec->ncntrs = i; in init_6120_cntrnames()
2488 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1; in init_6120_cntrnames()
2490 dd->cspec->cntrnamelen = 1 + s - cntr6120names; in init_6120_cntrnames()
2491 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), in init_6120_cntrnames()
2496 dd->cspec->nportcntrs = i - 1; in init_6120_cntrnames()
2497 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1; in init_6120_cntrnames()
2498 dd->cspec->portcntrs = kmalloc_array(dd->cspec->nportcntrs, in init_6120_cntrnames()
2509 ret = dd->cspec->cntrnamelen; in qib_read_6120cntrs()
2515 u64 *cntr = dd->cspec->cntrs; in qib_read_6120cntrs()
2518 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_6120cntrs()
2529 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_6120cntrs()
2542 ret = dd->cspec->portcntrnamelen; in qib_read_6120portcntrs()
2548 u64 *cntr = dd->cspec->portcntrs; in qib_read_6120portcntrs()
2549 struct qib_pportdata *ppd = &dd->pport[port]; in qib_read_6120portcntrs()
2552 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_6120portcntrs()
2559 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_6120portcntrs()
2580 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED)) in qib_chk_6120_errormask()
2585 if (errormask == dd->cspec->errormask) in qib_chk_6120_errormask()
2593 dd->cspec->errormask); in qib_chk_6120_errormask()
2595 if ((hwerrs & dd->cspec->hwerrmask) || in qib_chk_6120_errormask()
2599 /* force re-interrupt of pending events, just in case */ in qib_chk_6120_errormask()
2601 qib_devinfo(dd->pcidev, in qib_chk_6120_errormask()
2602 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n", in qib_chk_6120_errormask()
2603 fixed, errormask, (unsigned long)dd->cspec->errormask, in qib_chk_6120_errormask()
2609 * qib_get_6120_faststats - get word counters from chip before they overflow
2619 struct qib_pportdata *ppd = dd->pport; in qib_get_6120_faststats()
2627 if (!(dd->flags & QIB_INITTED) || dd->diag_client) in qib_get_6120_faststats()
2628 /* but re-arm the timer, for diags case; won't hurt other */ in qib_get_6120_faststats()
2633 * exceeding a threshold, so we need to check the word-counts in qib_get_6120_faststats()
2634 * even if they are 64-bit. in qib_get_6120_faststats()
2638 spin_lock_irqsave(&dd->eep_st_lock, flags); in qib_get_6120_faststats()
2639 traffic_wds -= dd->traffic_wds; in qib_get_6120_faststats()
2640 dd->traffic_wds += traffic_wds; in qib_get_6120_faststats()
2641 spin_unlock_irqrestore(&dd->eep_st_lock, flags); in qib_get_6120_faststats()
2645 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); in qib_get_6120_faststats()
2663 struct qib_devdata *dd = ppd->dd; in qib_6120_xgxs_reset()
2669 dd->control & ~QLOGIC_IB_C_LINKENABLE); in qib_6120_xgxs_reset()
2673 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_xgxs_reset()
2682 ret = ppd->link_width_active; in qib_6120_get_ib_cfg()
2686 ret = ppd->link_speed_active; in qib_6120_get_ib_cfg()
2690 ret = ppd->link_width_enabled; in qib_6120_get_ib_cfg()
2694 ret = ppd->link_speed_enabled; in qib_6120_get_ib_cfg()
2698 ret = ppd->vls_operational; in qib_6120_get_ib_cfg()
2710 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, in qib_6120_get_ib_cfg()
2715 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, in qib_6120_get_ib_cfg()
2721 ret = (ppd->dd->cspec->ibcctrl & in qib_6120_get_ib_cfg()
2735 ret = -EINVAL; in qib_6120_get_ib_cfg()
2746 struct qib_devdata *dd = ppd->dd; in qib_6120_set_ib_cfg()
2753 ppd->link_width_enabled = val; in qib_6120_set_ib_cfg()
2757 ppd->link_speed_enabled = val; in qib_6120_set_ib_cfg()
2761 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, in qib_6120_set_ib_cfg()
2764 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2766 dd->cspec->ibcctrl |= (u64) val << in qib_6120_set_ib_cfg()
2768 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2774 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, in qib_6120_set_ib_cfg()
2777 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2779 dd->cspec->ibcctrl |= (u64) val << in qib_6120_set_ib_cfg()
2781 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2787 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | in qib_6120_set_ib_cfg()
2788 ((u64) ppd->pkeys[2] << 32) | in qib_6120_set_ib_cfg()
2789 ((u64) ppd->pkeys[3] << 48); in qib_6120_set_ib_cfg()
2796 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2799 dd->cspec->ibcctrl |= in qib_6120_set_ib_cfg()
2801 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2813 val = (ppd->ibmaxlen >> 2) + 1; in qib_6120_set_ib_cfg()
2814 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen); in qib_6120_set_ib_cfg()
2815 dd->cspec->ibcctrl |= (u64)val << in qib_6120_set_ib_cfg()
2817 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2825 if (!dd->cspec->ibdeltainprog) { in qib_6120_set_ib_cfg()
2826 dd->cspec->ibdeltainprog = 1; in qib_6120_set_ib_cfg()
2827 dd->cspec->ibsymsnap = in qib_6120_set_ib_cfg()
2829 dd->cspec->iblnkerrsnap = in qib_6120_set_ib_cfg()
2843 ret = -EINVAL; in qib_6120_set_ib_cfg()
2865 ret = -EINVAL; in qib_6120_set_ib_cfg()
2874 ret = -EINVAL; in qib_6120_set_ib_cfg()
2878 ret = -EINVAL; in qib_6120_set_ib_cfg()
2889 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback); in qib_6120_set_loopback()
2890 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", in qib_6120_set_loopback()
2891 ppd->dd->unit, ppd->port); in qib_6120_set_loopback()
2893 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback); in qib_6120_set_loopback()
2894 qib_devinfo(ppd->dd->pcidev, in qib_6120_set_loopback()
2896 ppd->dd->unit, ppd->port); in qib_6120_set_loopback()
2898 ret = -EINVAL; in qib_6120_set_loopback()
2900 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl); in qib_6120_set_loopback()
2901 qib_write_kreg(ppd->dd, kr_scratch, 0); in qib_6120_set_loopback()
2909 struct qib_pportdata *ppd = cs->ppd; in pma_6120_timer()
2910 struct qib_ibport *ibp = &ppd->ibport_data; in pma_6120_timer()
2913 spin_lock_irqsave(&ibp->rvp.lock, flags); in pma_6120_timer()
2914 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) { in pma_6120_timer()
2915 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING; in pma_6120_timer()
2916 qib_snapshot_counters(ppd, &cs->sword, &cs->rword, in pma_6120_timer()
2917 &cs->spkts, &cs->rpkts, &cs->xmit_wait); in pma_6120_timer()
2918 mod_timer(&cs->pma_timer, in pma_6120_timer()
2919 jiffies + usecs_to_jiffies(ibp->rvp.pma_sample_interval)); in pma_6120_timer()
2920 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) { in pma_6120_timer()
2921 u64 ta, tb, tc, td, te; in pma_6120_timer() local
2923 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE; in pma_6120_timer()
2924 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te); in pma_6120_timer()
2926 cs->sword = ta - cs->sword; in pma_6120_timer()
2927 cs->rword = tb - cs->rword; in pma_6120_timer()
2928 cs->spkts = tc - cs->spkts; in pma_6120_timer()
2929 cs->rpkts = td - cs->rpkts; in pma_6120_timer()
2930 cs->xmit_wait = te - cs->xmit_wait; in pma_6120_timer()
2932 spin_unlock_irqrestore(&ibp->rvp.lock, flags); in pma_6120_timer()
2936 * Note that the caller has the ibp->rvp.lock held.
2941 struct qib_chip_specific *cs = ppd->dd->cspec; in qib_set_cntr_6120_sample()
2944 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED; in qib_set_cntr_6120_sample()
2945 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start)); in qib_set_cntr_6120_sample()
2947 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING; in qib_set_cntr_6120_sample()
2948 qib_snapshot_counters(ppd, &cs->sword, &cs->rword, in qib_set_cntr_6120_sample()
2949 &cs->spkts, &cs->rpkts, &cs->xmit_wait); in qib_set_cntr_6120_sample()
2950 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv)); in qib_set_cntr_6120_sample()
2952 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE; in qib_set_cntr_6120_sample()
2953 cs->sword = 0; in qib_set_cntr_6120_sample()
2954 cs->rword = 0; in qib_set_cntr_6120_sample()
2955 cs->spkts = 0; in qib_set_cntr_6120_sample()
2956 cs->rpkts = 0; in qib_set_cntr_6120_sample()
2957 cs->xmit_wait = 0; in qib_set_cntr_6120_sample()
2996 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_6120_ib_updown()
2997 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; in qib_6120_ib_updown()
2998 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_6120_ib_updown()
3001 if (ppd->dd->cspec->ibdeltainprog) { in qib_6120_ib_updown()
3002 ppd->dd->cspec->ibdeltainprog = 0; in qib_6120_ib_updown()
3003 ppd->dd->cspec->ibsymdelta += in qib_6120_ib_updown()
3004 read_6120_creg32(ppd->dd, cr_ibsymbolerr) - in qib_6120_ib_updown()
3005 ppd->dd->cspec->ibsymsnap; in qib_6120_ib_updown()
3006 ppd->dd->cspec->iblnkerrdelta += in qib_6120_ib_updown()
3007 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) - in qib_6120_ib_updown()
3008 ppd->dd->cspec->iblnkerrsnap; in qib_6120_ib_updown()
3012 ppd->dd->cspec->lli_counter = 0; in qib_6120_ib_updown()
3013 if (!ppd->dd->cspec->ibdeltainprog) { in qib_6120_ib_updown()
3014 ppd->dd->cspec->ibdeltainprog = 1; in qib_6120_ib_updown()
3015 ppd->dd->cspec->ibsymsnap = in qib_6120_ib_updown()
3016 read_6120_creg32(ppd->dd, cr_ibsymbolerr); in qib_6120_ib_updown()
3017 ppd->dd->cspec->iblnkerrsnap = in qib_6120_ib_updown()
3018 read_6120_creg32(ppd->dd, cr_iblinkerrrecov); in qib_6120_ib_updown()
3043 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_6120_mod()
3044 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_6120_mod()
3045 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_6120_mod()
3046 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_6120_mod()
3048 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_6120_mod()
3050 dd->cspec->gpio_out = new_out; in gpio_6120_mod()
3051 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_6120_mod()
3076 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_6120_chip_params()
3078 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_6120_chip_params()
3079 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_6120_chip_params()
3080 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_6120_chip_params()
3081 dd->palign = qib_read_kreg32(dd, kr_palign); in get_6120_chip_params()
3082 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); in get_6120_chip_params()
3083 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; in get_6120_chip_params()
3085 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in get_6120_chip_params()
3088 dd->piosize2k = val & ~0U; in get_6120_chip_params()
3089 dd->piosize4k = val >> 32; in get_6120_chip_params()
3092 if (mtu == -1) in get_6120_chip_params()
3094 dd->pport->ibmtu = (u32)mtu; in get_6120_chip_params()
3097 dd->piobcnt2k = val & ~0U; in get_6120_chip_params()
3098 dd->piobcnt4k = val >> 32; in get_6120_chip_params()
3099 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1; in get_6120_chip_params()
3101 dd->pio2kbase = (u32 __iomem *) in get_6120_chip_params()
3102 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase); in get_6120_chip_params()
3103 if (dd->piobcnt4k) { in get_6120_chip_params()
3104 dd->pio4kbase = (u32 __iomem *) in get_6120_chip_params()
3105 (((char __iomem *) dd->kregbase) + in get_6120_chip_params()
3106 (dd->piobufbase >> 32)); in get_6120_chip_params()
3112 dd->align4k = ALIGN(dd->piosize4k, dd->palign); in get_6120_chip_params()
3115 piobufs = dd->piobcnt4k + dd->piobcnt2k; in get_6120_chip_params()
3117 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / in get_6120_chip_params()
3131 dd->cspec->cregbase = (u64 __iomem *) in set_6120_baseaddrs()
3132 ((char __iomem *) dd->kregbase + cregbase); in set_6120_baseaddrs()
3134 dd->egrtidbase = (u64 __iomem *) in set_6120_baseaddrs()
3135 ((char __iomem *) dd->kregbase + dd->rcvegrbase); in set_6120_baseaddrs()
3148 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); in qib_late_6120_initreg()
3149 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); in qib_late_6120_initreg()
3150 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); in qib_late_6120_initreg()
3151 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); in qib_late_6120_initreg()
3153 if (val != dd->pioavailregs_phys) { in qib_late_6120_initreg()
3156 (unsigned long) dd->pioavailregs_phys, in qib_late_6120_initreg()
3158 ret = -EINVAL; in qib_late_6120_initreg()
3170 dd->pport = ppd; in init_6120_variables()
3171 dd->num_pports = 1; in init_6120_variables()
3173 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports); in init_6120_variables()
3174 dd->cspec->ppd = ppd; in init_6120_variables()
3175 ppd->cpspec = NULL; /* not used in this chip */ in init_6120_variables()
3177 spin_lock_init(&dd->cspec->kernel_tid_lock); in init_6120_variables()
3178 spin_lock_init(&dd->cspec->user_tid_lock); in init_6120_variables()
3179 spin_lock_init(&dd->cspec->rcvmod_lock); in init_6120_variables()
3180 spin_lock_init(&dd->cspec->gpio_lock); in init_6120_variables()
3183 dd->revision = readq(&dd->kregbase[kr_revision]); in init_6120_variables()
3185 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { in init_6120_variables()
3188 ret = -ENODEV; in init_6120_variables()
3191 dd->flags |= QIB_PRESENT; /* now register routines work */ in init_6120_variables()
3193 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, in init_6120_variables()
3195 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, in init_6120_variables()
3205 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; in init_6120_variables()
3206 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; in init_6120_variables()
3207 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV; in init_6120_variables()
3210 dd->flags |= QIB_PIO_FLUSH_WC; in init_6120_variables()
3215 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; in init_6120_variables()
3216 ppd->link_speed_supported = QIB_IB_SDR; in init_6120_variables()
3217 ppd->link_width_enabled = IB_WIDTH_4X; in init_6120_variables()
3218 ppd->link_speed_enabled = ppd->link_speed_supported; in init_6120_variables()
3220 ppd->link_width_active = ppd->link_width_enabled; in init_6120_variables()
3221 ppd->link_speed_active = ppd->link_speed_enabled; in init_6120_variables()
3222 ppd->vls_supported = IB_VL_VL0; in init_6120_variables()
3223 ppd->vls_operational = ppd->vls_supported; in init_6120_variables()
3225 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE; in init_6120_variables()
3226 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE; in init_6120_variables()
3227 dd->rhf_offset = 0; in init_6120_variables()
3231 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU; in init_6120_variables()
3232 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); in init_6120_variables()
3241 dd->rhdrhead_intr_off = 1ULL << 32; in init_6120_variables()
3244 timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0); in init_6120_variables()
3245 timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0); in init_6120_variables()
3247 dd->ureg_align = qib_read_kreg32(dd, kr_palign); in init_6120_variables()
3249 dd->piosize2kmax_dwords = dd->piosize2k >> 2; in init_6120_variables()
3268 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16; in init_6120_variables()
3270 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs; in init_6120_variables()
3271 dd->pbufsctxt = dd->lastctxt_piobuf / in init_6120_variables()
3272 (dd->cfgctxts - dd->first_user_ctxt); in init_6120_variables()
3298 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1; in get_6120_link_buf()
3304 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in get_6120_link_buf()
3305 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ in get_6120_link_buf()
3306 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); in get_6120_link_buf()
3312 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */ in get_6120_link_buf()
3313 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ in get_6120_link_buf()
3314 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); in get_6120_link_buf()
3323 struct qib_devdata *dd = ppd->dd; in qib_6120_getsendbuf()
3327 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE))) in qib_6120_getsendbuf()
3331 if ((plen + 1) > dd->piosize2kmax_dwords) in qib_6120_getsendbuf()
3332 first = dd->piobcnt2k; in qib_6120_getsendbuf()
3336 last = dd->piobcnt2k + dd->piobcnt4k - 1; in qib_6120_getsendbuf()
3344 return -ENODEV; in init_sdma_6120_regs()
3385 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt; in qib_6120_init_ctxt()
3386 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt; in qib_6120_init_ctxt()
3401 return -ENXIO; in qib_6120_tempsense_rd()
3418 * qib_init_iba6120_funcs - set up the chip-specific function pointers
3423 * chip-specific function pointers for later use.
3425 * It also allocates/partially-inits the qib_devdata struct for
3439 dd->f_bringup_serdes = qib_6120_bringup_serdes; in qib_init_iba6120_funcs()
3440 dd->f_cleanup = qib_6120_setup_cleanup; in qib_init_iba6120_funcs()
3441 dd->f_clear_tids = qib_6120_clear_tids; in qib_init_iba6120_funcs()
3442 dd->f_free_irq = qib_free_irq; in qib_init_iba6120_funcs()
3443 dd->f_get_base_info = qib_6120_get_base_info; in qib_init_iba6120_funcs()
3444 dd->f_get_msgheader = qib_6120_get_msgheader; in qib_init_iba6120_funcs()
3445 dd->f_getsendbuf = qib_6120_getsendbuf; in qib_init_iba6120_funcs()
3446 dd->f_gpio_mod = gpio_6120_mod; in qib_init_iba6120_funcs()
3447 dd->f_eeprom_wen = qib_6120_eeprom_wen; in qib_init_iba6120_funcs()
3448 dd->f_hdrqempty = qib_6120_hdrqempty; in qib_init_iba6120_funcs()
3449 dd->f_ib_updown = qib_6120_ib_updown; in qib_init_iba6120_funcs()
3450 dd->f_init_ctxt = qib_6120_init_ctxt; in qib_init_iba6120_funcs()
3451 dd->f_initvl15_bufs = qib_6120_initvl15_bufs; in qib_init_iba6120_funcs()
3452 dd->f_intr_fallback = qib_6120_nointr_fallback; in qib_init_iba6120_funcs()
3453 dd->f_late_initreg = qib_late_6120_initreg; in qib_init_iba6120_funcs()
3454 dd->f_setpbc_control = qib_6120_setpbc_control; in qib_init_iba6120_funcs()
3455 dd->f_portcntr = qib_portcntr_6120; in qib_init_iba6120_funcs()
3456 dd->f_put_tid = (dd->minrev >= 2) ? in qib_init_iba6120_funcs()
3459 dd->f_quiet_serdes = qib_6120_quiet_serdes; in qib_init_iba6120_funcs()
3460 dd->f_rcvctrl = rcvctrl_6120_mod; in qib_init_iba6120_funcs()
3461 dd->f_read_cntrs = qib_read_6120cntrs; in qib_init_iba6120_funcs()
3462 dd->f_read_portcntrs = qib_read_6120portcntrs; in qib_init_iba6120_funcs()
3463 dd->f_reset = qib_6120_setup_reset; in qib_init_iba6120_funcs()
3464 dd->f_init_sdma_regs = init_sdma_6120_regs; in qib_init_iba6120_funcs()
3465 dd->f_sdma_busy = qib_sdma_6120_busy; in qib_init_iba6120_funcs()
3466 dd->f_sdma_gethead = qib_sdma_6120_gethead; in qib_init_iba6120_funcs()
3467 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl; in qib_init_iba6120_funcs()
3468 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt; in qib_init_iba6120_funcs()
3469 dd->f_sdma_update_tail = qib_sdma_update_6120_tail; in qib_init_iba6120_funcs()
3470 dd->f_sendctrl = sendctrl_6120_mod; in qib_init_iba6120_funcs()
3471 dd->f_set_armlaunch = qib_set_6120_armlaunch; in qib_init_iba6120_funcs()
3472 dd->f_set_cntr_sample = qib_set_cntr_6120_sample; in qib_init_iba6120_funcs()
3473 dd->f_iblink_state = qib_6120_iblink_state; in qib_init_iba6120_funcs()
3474 dd->f_ibphys_portstate = qib_6120_phys_portstate; in qib_init_iba6120_funcs()
3475 dd->f_get_ib_cfg = qib_6120_get_ib_cfg; in qib_init_iba6120_funcs()
3476 dd->f_set_ib_cfg = qib_6120_set_ib_cfg; in qib_init_iba6120_funcs()
3477 dd->f_set_ib_loopback = qib_6120_set_loopback; in qib_init_iba6120_funcs()
3478 dd->f_set_intr_state = qib_6120_set_intr_state; in qib_init_iba6120_funcs()
3479 dd->f_setextled = qib_6120_setup_setextled; in qib_init_iba6120_funcs()
3480 dd->f_txchk_change = qib_6120_txchk_change; in qib_init_iba6120_funcs()
3481 dd->f_update_usrhead = qib_update_6120_usrhead; in qib_init_iba6120_funcs()
3482 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr; in qib_init_iba6120_funcs()
3483 dd->f_xgxs_reset = qib_6120_xgxs_reset; in qib_init_iba6120_funcs()
3484 dd->f_writescratch = writescratch; in qib_init_iba6120_funcs()
3485 dd->f_tempsense_rd = qib_6120_tempsense_rd; in qib_init_iba6120_funcs()
3487 dd->f_notify_dca = qib_6120_notify_dca; in qib_init_iba6120_funcs()
3500 /* initialize chip-specific variables */ in qib_init_iba6120_funcs()