3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
8  * General Public License (GPL) Version 2, available from the file
16  *      - Redistributions of source code must retain the above
20  *      - Redistributions in binary form must reproduce the above
60  * Each client that opens the diag device must read then write
85 		client_pool = dc->next;  in get_client()
91 		dc->next = NULL;  in get_client()
92 		dc->dd = dd;  in get_client()
93 		dc->pid = current->pid;  in get_client()
94 		dc->state = OPENED;  in get_client()
104 	struct qib_devdata *dd = dc->dd;  in return_client()
108 	if (dc == dd->diag_client) {  in return_client()
109 		dd->diag_client = dc->next;  in return_client()
112 		tdc = dc->dd->diag_client;  in return_client()
114 			if (dc == tdc->next) {  in return_client()
115 				tdc->next = dc->next;  in return_client()
119 			tdc = tdc->next;  in return_client()
123 		rdc->state = UNUSED;  in return_client()
124 		rdc->dd = NULL;  in return_client()
125 		rdc->pid = 0;  in return_client()
126 		rdc->next = client_pool;  in return_client()
173 	snprintf(name, sizeof(name), "ipath_diag%d", dd->unit);  in qib_diag_add()
174 	ret = qib_cdev_init(QIB_DIAG_MINOR_BASE + dd->unit, name,  in qib_diag_add()
175 			    &diag_file_ops, &dd->diag_cdev,  in qib_diag_add()
176 			    &dd->diag_device);  in qib_diag_add()
190 	qib_cdev_cleanup(&dd->diag_cdev, &dd->diag_device);  in qib_diag_remove()
196 	while (dd->diag_client)  in qib_diag_remove()
197 		return_client(dd->diag_client);  in qib_diag_remove()
202 		client_pool = dc->next;  in qib_diag_remove()
209 /* qib_remap_ioaddr32 - remap an offset into chip address space to __iomem *
212  * @offs: the offset in chip-space
214  * This returns a u32 __iomem * so it can be used for both 64 and 32-bit
216  * write-combining, the logically contiguous address-space of the chip
217  * may be split into virtually non-contiguous spaces, with different
224  *		- kregs + sregs + cregs + uregs (in any order)
225  *		- piobufs (2K and 4K bufs in either order)
227  *		- kregs + sregs + cregs (in any order)
228  *		- piobufs (2K and 4K bufs in either order)
229  *		- uregs
231  * If cntp is non-NULL, returns how many bytes from offset can be accessed
239 	u32 __iomem *krb32 = (u32 __iomem *)dd->kregbase;  in qib_remap_ioaddr32()
245 	kreglen = (dd->kregend - dd->kregbase) * sizeof(u64);  in qib_remap_ioaddr32()
248 		cnt = kreglen - offset;  in qib_remap_ioaddr32()
257 	if (dd->userbase) {  in qib_remap_ioaddr32()
259 		u32 ulim = (dd->cfgctxts * dd->ureg_align) + dd->uregbase;  in qib_remap_ioaddr32()
261 		if (!dd->piovl15base)  in qib_remap_ioaddr32()
262 			snd_lim = dd->uregbase;  in qib_remap_ioaddr32()
263 		krb32 = (u32 __iomem *)dd->userbase;  in qib_remap_ioaddr32()
264 		if (offset >= dd->uregbase && offset < ulim) {  in qib_remap_ioaddr32()
265 			map = krb32 + (offset - dd->uregbase) / sizeof(u32);  in qib_remap_ioaddr32()
266 			cnt = ulim - offset;  in qib_remap_ioaddr32()
275 	 * chip-specific code here, so should not make many assumptions.  in qib_remap_ioaddr32()
281 	snd_bottom = dd->pio2k_bufbase;  in qib_remap_ioaddr32()
283 		u32 tot2k = dd->piobcnt2k * ALIGN(dd->piosize2k, dd->palign);  in qib_remap_ioaddr32()
290 	tot4k = dd->piobcnt4k * dd->align4k;  in qib_remap_ioaddr32()
291 	offs4k = dd->piobufbase >> 32;  in qib_remap_ioaddr32()
292 	if (dd->piobcnt4k) {  in qib_remap_ioaddr32()
297 			if (!dd->userbase || dd->piovl15base)  in qib_remap_ioaddr32()
306 		offset -= snd_bottom;  in qib_remap_ioaddr32()
307 		map = (u32 __iomem *)dd->piobase + (offset / sizeof(u32));  in qib_remap_ioaddr32()
308 		cnt = snd_lim - offset;  in qib_remap_ioaddr32()
311 	if (!map && offs4k && dd->piovl15base) {  in qib_remap_ioaddr32()
312 		snd_lim = offs4k + tot4k + 2 * dd->align4k;  in qib_remap_ioaddr32()
314 			map = (u32 __iomem *)dd->piovl15base +  in qib_remap_ioaddr32()
315 				((offset - (offs4k + tot4k)) / sizeof(u32));  in qib_remap_ioaddr32()
316 			cnt = snd_lim - offset;  in qib_remap_ioaddr32()
327  * qib_read_umem64 - read a 64-bit quantity from the chip into user space
337  * NOTE:  This assumes the chip address is 64-bit aligned.
348 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_read_umem64()
349 		ret = -EINVAL;  in qib_read_umem64()
361 			ret = -EFAULT;  in qib_read_umem64()
373  * qib_write_umem64 - write a 64-bit quantity to the chip from user space
380  * NOTE:  This assumes the chip address is 64-bit aligned.
392 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_write_umem64()
393 		ret = -EINVAL;  in qib_write_umem64()
405 			ret = -EFAULT;  in qib_write_umem64()
419  * qib_read_umem32 - read a 32-bit quantity from the chip into user space
437 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_read_umem32()
438 		ret = -EINVAL;  in qib_read_umem32()
450 			ret = -EFAULT;  in qib_read_umem32()
464  * qib_write_umem32 - write a 32-bit quantity to the chip from user space
483 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_write_umem32()
484 		ret = -EINVAL;  in qib_write_umem32()
495 			ret = -EFAULT;  in qib_write_umem32()
510 	int unit = iminor(in) - QIB_DIAG_MINOR_BASE;  in qib_diag_open()
519 	if (dd == NULL || !(dd->flags & QIB_PRESENT) ||  in qib_diag_open()
520 	    !dd->kregbase) {  in qib_diag_open()
521 		ret = -ENODEV;  in qib_diag_open()
527 		ret = -ENOMEM;  in qib_diag_open()
530 	dc->next = dd->diag_client;  in qib_diag_open()
531 	dd->diag_client = dc;  in qib_diag_open()
532 	fp->private_data = dc;  in qib_diag_open()
541  * qib_diagpkt_write - write an IB packet
542  * @fp: the diag data device file pointer
560 		ret = -EINVAL;  in qib_diagpkt_write()
564 		ret = -EFAULT;  in qib_diagpkt_write()
569 	if (!dd || !(dd->flags & QIB_PRESENT) || !dd->kregbase) {  in qib_diagpkt_write()
570 		ret = -ENODEV;  in qib_diagpkt_write()
573 	if (!(dd->flags & QIB_INITTED)) {  in qib_diagpkt_write()
575 		ret = -ENODEV;  in qib_diagpkt_write()
579 	if (dp.version != _DIAG_XPKT_VERS) {  in qib_diagpkt_write()
580 		qib_dev_err(dd, "Invalid version %u for diagpkt_write\n",  in qib_diagpkt_write()
581 			    dp.version);  in qib_diagpkt_write()
582 		ret = -EINVAL;  in qib_diagpkt_write()
587 		ret = -EINVAL;  in qib_diagpkt_write()
590 	if (!dp.port || dp.port > dd->num_pports) {  in qib_diagpkt_write()
591 		ret = -EINVAL;  in qib_diagpkt_write()
594 	ppd = &dd->pport[dp.port - 1];  in qib_diagpkt_write()
603 	if (dp.len > ppd->ibmaxlen - maxlen_reserve) {  in qib_diagpkt_write()
604 		ret = -EINVAL;  in qib_diagpkt_write()
612 		ret = -ENOMEM;  in qib_diagpkt_write()
619 		ret = -EFAULT;  in qib_diagpkt_write()
628 	piobuf = dd->f_getsendbuf(ppd, dp.pbc_wd, &pbufn);  in qib_diagpkt_write()
630 		ret = -EBUSY;  in qib_diagpkt_write()
634 	dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbufn));  in qib_diagpkt_write()
637 	dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_DIS1, NULL);  in qib_diagpkt_write()
645 	if (dd->flags & QIB_PIO_FLUSH_WC) {  in qib_diagpkt_write()
647 		qib_pio_copy(piobuf + 2, tmpbuf, plen - 1);  in qib_diagpkt_write()
649 		__raw_writel(tmpbuf[plen - 1], piobuf + plen + 1);  in qib_diagpkt_write()
653 	if (dd->flags & QIB_USE_SPCL_TRIG) {  in qib_diagpkt_write()
654 		u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;  in qib_diagpkt_write()
661 	 * Ensure buffer is written to the chip, then re-enable  in qib_diagpkt_write()
667 	dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_ENAB1, NULL);  in qib_diagpkt_write()
679 	return_client(fp->private_data);  in qib_diag_release()
680 	fp->private_data = NULL;  in qib_diag_release()
686  * Chip-specific code calls to register its interest in
701 		return -EINVAL;  in qib_register_observer()
704 		return -ENOMEM;  in qib_register_observer()
706 	spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_register_observer()
707 	olp->op = op;  in qib_register_observer()
708 	olp->next = dd->diag_observer_list;  in qib_register_observer()
709 	dd->diag_observer_list = olp;  in qib_register_observer()
710 	spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_register_observer()
721 	spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
722 	olp = dd->diag_observer_list;  in qib_unregister_observers()
725 		dd->diag_observer_list = olp->next;  in qib_unregister_observers()
726 		spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
729 		spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
730 		olp = dd->diag_observer_list;  in qib_unregister_observers()
732 	spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
737  * is simple stack of observers. This must be called with diag transaction
746 	olp = dd->diag_observer_list;  in diag_get_observer()
748 		op = olp->op;  in diag_get_observer()
749 		if (addr >= op->bottom && addr <= op->top)  in diag_get_observer()
751 		olp = olp->next;  in diag_get_observer()
762 	struct qib_diag_client *dc = fp->private_data;  in qib_diag_read()
763 	struct qib_devdata *dd = dc->dd;  in qib_diag_read()
766 	if (dc->pid != current->pid) {  in qib_diag_read()
767 		ret = -EPERM;  in qib_diag_read()
774 		/* address or length is not 32-bit aligned, hence invalid */  in qib_diag_read()
775 		ret = -EINVAL;  in qib_diag_read()
776 	else if (dc->state < READY && (*off || count != 8))  in qib_diag_read()
777 		ret = -EINVAL;  /* prevent cat /dev/qib_diag* */  in qib_diag_read()
785 		ret = -1;  in qib_diag_read()
786 		spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_diag_read()
789 		 * we only support a single 32 or 64-bit read  in qib_diag_read()
796 			ret = op->hook(dd, op, offset, &data64, 0, use_32);  in qib_diag_read()
802 		spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_diag_read()
806 				 * Address or length is not 64-bit aligned;  in qib_diag_read()
807 				 * do 32-bit rd  in qib_diag_read()
819 				ret = -EFAULT;  in qib_diag_read()
826 		if (dc->state == OPENED)  in qib_diag_read()
827 			dc->state = INIT;  in qib_diag_read()
836 	struct qib_diag_client *dc = fp->private_data;  in qib_diag_write()
837 	struct qib_devdata *dd = dc->dd;  in qib_diag_write()
840 	if (dc->pid != current->pid) {  in qib_diag_write()
841 		ret = -EPERM;  in qib_diag_write()
848 		/* address or length is not 32-bit aligned, hence invalid */  in qib_diag_write()
849 		ret = -EINVAL;  in qib_diag_write()
850 	else if (dc->state < READY &&  in qib_diag_write()
851 		((*off || count != 8) || dc->state != INIT))  in qib_diag_write()
852 		/* No writes except second-step of init seq */  in qib_diag_write()
853 		ret = -EINVAL;  /* before any other write allowed */  in qib_diag_write()
861 		 * We only support a single 32 or 64-bit write  in qib_diag_write()
864 		 * to make "diag transaction" meaningful when we  in qib_diag_write()
873 				ret = -EFAULT;  in qib_diag_write()
876 			spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_diag_write()
879 				ret = op->hook(dd, op, offset, &data64, ~0Ull,  in qib_diag_write()
881 			spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_diag_write()
887 				 * Address or length is not 64-bit aligned;  in qib_diag_write()
888 				 * do 32-bit write  in qib_diag_write()
901 		if (dc->state == INIT)  in qib_diag_write()
902 			dc->state = READY; /* all read/write OK now */  in qib_diag_write()