Lines Matching +full:0 +full:- +full:63

1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
7 #define IRDMA_E_UDA_SQ_L4T_UNKNOWN	0
13 #define IRDMA_E_UDA_SQ_IIPT_UNKNOWN		0
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
43 /* Byte Offset 0 */
73 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0)
74 #define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0)
80 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
83 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
85 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
88 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0)
89 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32)
90 #define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0)
91 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32)
92 #define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0)
93 #define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63)
97 #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0)
105 #define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0)
106 #define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63)
108 #define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0)
111 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0)
113 #define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0)
115 #define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0)
117 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
118 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
119 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
120 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
121 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
122 #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)