Lines Matching +full:0 +full:- +full:63
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
17 #define IRDMA_IRD_HW_SIZE_4 0
24 IRDMA_ANY_PROTOCOL = 0,
29 #define IRDMA_QP_STATE_INVALID 0
55 #define RDMA_OPCODE_M 0x0f
58 #define CQE_MAJOR_DRV 0x8000
69 #define IRDMA_AE_SOURCE_RSVD 0x0
70 #define IRDMA_AE_SOURCE_RQ 0x1
71 #define IRDMA_AE_SOURCE_RQ_0011 0x3
73 #define IRDMA_AE_SOURCE_CQ 0x2
74 #define IRDMA_AE_SOURCE_CQ_0110 0x6
75 #define IRDMA_AE_SOURCE_CQ_1010 0xa
76 #define IRDMA_AE_SOURCE_CQ_1110 0xe
78 #define IRDMA_AE_SOURCE_SQ 0x5
79 #define IRDMA_AE_SOURCE_SQ_0111 0x7
81 #define IRDMA_AE_SOURCE_IN_RR_WR 0x9
82 #define IRDMA_AE_SOURCE_IN_RR_WR_1011 0xb
83 #define IRDMA_AE_SOURCE_OUT_RR 0xd
84 #define IRDMA_AE_SOURCE_OUT_RR_1111 0xf
86 #define IRDMA_TCP_STATE_NON_EXISTENT 0
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
125 #define IRDMAQP_TERM_SEND_TERM_AND_FIN 0
137 #define IRDMA_CQE_QTYPE_RQ 0
152 #define IRDMAQP_OP_RDMA_WRITE 0x00
153 #define IRDMAQP_OP_RDMA_READ 0x01
154 #define IRDMAQP_OP_RDMA_SEND 0x03
155 #define IRDMAQP_OP_RDMA_SEND_INV 0x04
156 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05
157 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06
158 #define IRDMAQP_OP_BIND_MW 0x08
159 #define IRDMAQP_OP_FAST_REGISTER 0x09
160 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a
161 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b
162 #define IRDMAQP_OP_NOP 0x0c
163 #define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d
164 #define IRDMAQP_OP_GEN_RTS_AE 0x30
221 #define IRDMA_CQP_OP_CREATE_QP 0
222 #define IRDMA_CQP_OP_MODIFY_QP 0x1
223 #define IRDMA_CQP_OP_DESTROY_QP 0x02
224 #define IRDMA_CQP_OP_CREATE_CQ 0x03
225 #define IRDMA_CQP_OP_MODIFY_CQ 0x04
226 #define IRDMA_CQP_OP_DESTROY_CQ 0x05
227 #define IRDMA_CQP_OP_ALLOC_STAG 0x09
228 #define IRDMA_CQP_OP_REG_MR 0x0a
229 #define IRDMA_CQP_OP_QUERY_STAG 0x0b
230 #define IRDMA_CQP_OP_REG_SMR 0x0c
231 #define IRDMA_CQP_OP_DEALLOC_STAG 0x0d
232 #define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e
233 #define IRDMA_CQP_OP_MANAGE_ARP 0x0f
234 #define IRDMA_CQP_OP_MANAGE_VF_PBLE_BP 0x10
235 #define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11
236 #define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12
237 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13
238 #define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14
239 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13
240 #define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15
241 #define IRDMA_CQP_OP_CREATE_CEQ 0x16
242 #define IRDMA_CQP_OP_DESTROY_CEQ 0x18
243 #define IRDMA_CQP_OP_CREATE_AEQ 0x19
244 #define IRDMA_CQP_OP_DESTROY_AEQ 0x1b
245 #define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c
246 #define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d
247 #define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e
248 #define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f
249 #define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20
250 #define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21
251 #define IRDMA_CQP_OP_FLUSH_WQES 0x22
253 #define IRDMA_CQP_OP_GEN_AE 0x22
254 #define IRDMA_CQP_OP_MANAGE_APBVT 0x23
255 #define IRDMA_CQP_OP_NOP 0x24
256 #define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
257 #define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26
258 #define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27
259 #define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28
260 #define IRDMA_CQP_OP_SUSPEND_QP 0x29
261 #define IRDMA_CQP_OP_RESUME_QP 0x2a
262 #define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b
263 #define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c
264 #define IRDMA_CQP_OP_MANAGE_STATS 0x2d
265 #define IRDMA_CQP_OP_GATHER_STATS 0x2e
266 #define IRDMA_CQP_OP_UP_MAP 0x2f
269 #define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102
270 #define IRDMA_AE_AMP_INVALID_STAG 0x0103
271 #define IRDMA_AE_AMP_BAD_QP 0x0104
272 #define IRDMA_AE_AMP_BAD_PD 0x0105
273 #define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106
274 #define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107
275 #define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108
276 #define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109
277 #define IRDMA_AE_AMP_TO_WRAP 0x010a
278 #define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c
279 #define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d
280 #define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e
281 #define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110
282 #define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111
283 #define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112
284 #define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113
285 #define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114
286 #define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115
287 #define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116
288 #define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117
289 #define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118
290 #define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
291 #define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
292 #define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b
293 #define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c
294 #define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d
295 #define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e
296 #define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f
297 #define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120
298 #define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121
299 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132
300 #define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133
301 #define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134
302 #define IRDMA_AE_UDA_L4LEN_INVALID 0x0135
303 #define IRDMA_AE_BAD_CLOSE 0x0201
304 #define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
305 #define IRDMA_AE_CQ_OPERATION_ERROR 0x0203
306 #define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
307 #define IRDMA_AE_STAG_ZERO_INVALID 0x0206
308 #define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207
309 #define IRDMA_AE_IB_INVALID_REQUEST 0x0208
310 #define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a
311 #define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b
312 #define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c
313 #define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d
314 #define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e
315 #define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220
316 #define IRDMA_AE_INVALID_REQUEST 0x0223
317 #define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
318 #define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
319 #define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
320 #define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305
321 #define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306
322 #define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307
323 #define IRDMA_AE_DDP_NO_L_BIT 0x0308
324 #define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311
325 #define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312
326 #define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313
327 #define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314
328 #define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316
329 #define IRDMA_AE_ROCE_EMPTY_MCG 0x0380
330 #define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381
331 #define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382
332 #define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383
333 #define IRDMA_AE_INVALID_ARP_ENTRY 0x0401
334 #define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402
335 #define IRDMA_AE_STALE_ARP_ENTRY 0x0403
336 #define IRDMA_AE_INVALID_AH_ENTRY 0x0406
337 #define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501
338 #define IRDMA_AE_LLP_CONNECTION_RESET 0x0502
339 #define IRDMA_AE_LLP_FIN_RECEIVED 0x0503
340 #define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504
341 #define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
342 #define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507
343 #define IRDMA_AE_LLP_SYN_RECEIVED 0x0508
344 #define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509
345 #define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a
346 #define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b
347 #define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c
348 #define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e
349 #define IRDMA_AE_LLP_TOO_MANY_RNRS 0x050f
350 #define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520
351 #define IRDMA_AE_RESET_SENT 0x0601
352 #define IRDMA_AE_TERMINATE_SENT 0x0602
353 #define IRDMA_AE_RESET_NOT_SENT 0x0603
354 #define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700
355 #define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
356 #define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702
357 #define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
368 #define IRDMA_MAX_STATS_24 0xffffffULL
369 #define IRDMA_MAX_STATS_32 0xffffffffULL
370 #define IRDMA_MAX_STATS_48 0xffffffffffffULL
371 #define IRDMA_MAX_STATS_56 0xffffffffffffffULL
372 #define IRDMA_MAX_STATS_64 0xffffffffffffffffULL
374 #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
377 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
379 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
380 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
383 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
384 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
390 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
395 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
396 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(5, 0)
397 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
408 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
412 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
416 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
418 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
419 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
423 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
430 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
432 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
433 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
436 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
437 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
439 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
447 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
449 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
451 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
452 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
453 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
454 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
462 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
464 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
472 #define IRDMA_CQ_VALID BIT_ULL(63)
476 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
477 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
479 #define IRDMA_CQ_IMMDATA_S 0
480 #define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S)
481 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
482 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
483 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
484 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
485 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
488 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
495 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
496 #define IRDMA_CEQE_VALID BIT_ULL(63)
500 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
509 #define IRDMA_AEQE_VALID BIT_ULL(63)
515 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
516 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
522 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
525 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
528 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
530 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
531 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
545 #define IRDMA_CQPSQ_QP_QPID_S 0
546 #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
569 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
570 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
571 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
581 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
585 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
586 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
603 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
605 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
607 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
610 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
616 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
617 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
618 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
622 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
626 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
628 /* Manage Push Page - MPP */
629 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
630 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
632 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
633 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
638 /* Upload Context - UCTX */
640 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
646 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
649 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
651 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
652 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
657 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
658 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
661 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
663 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
666 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
667 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
669 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
672 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
673 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
678 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
680 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
681 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
682 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
683 #define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
684 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
686 #define IRDMA_CQPSQ_UPESD_BM_PF 0
691 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
693 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
694 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
695 #define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0)
697 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
698 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
700 #define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000
701 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
702 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
703 #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
704 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
727 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
728 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
732 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
739 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
740 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
741 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
742 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
743 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
747 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
748 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
756 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
760 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
761 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
764 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
765 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
766 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
768 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
770 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
771 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
772 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
773 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
774 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
775 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
776 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
778 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
779 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
780 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
781 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
783 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
784 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
786 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
787 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
790 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
792 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
793 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
794 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
795 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
796 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
811 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
813 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
823 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
827 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
828 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
829 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
830 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
831 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
833 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
835 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
848 #define IRDMAQPSQ_VALID BIT_ULL(63)
851 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
853 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
854 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
855 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
856 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
857 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
859 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
867 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
868 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
877 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
878 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
882 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
884 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
889 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
890 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
891 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
892 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
906 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
907 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
908 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
910 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
911 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
912 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
915 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
916 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
917 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
918 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)
922 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
927 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
932 (_ceq)->ceqe_base[_pos].buf \
940 #define IRDMA_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)
944 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
949 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
954 (_ring).head = 0; \
955 (_ring).tail = 0; \
968 (_retcode) = 0; \
970 (_retcode) = -ENOMEM; \
979 (_retcode) = 0; \
981 (_retcode) = -ENOMEM; \
990 (_retcode) = 0; \
992 (_retcode) = -ENOMEM; \
999 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1001 (_retcode) = 0; \
1003 (_retcode) = -ENOMEM; \
1023 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1028 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1033 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1038 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1043 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1047 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1051 (IRDMA_RING_USED_QUANTA(_ring) != 0) \
1056 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1061 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1066 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1084 IRDMA_ADD_NODE = 0,
1089 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1090 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1091 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1092 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1093 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1094 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1095 IRDMA_SHADOWAREA_M = (128 - 1),
1096 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1097 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1101 IRDMA_CQP_ALIGNMENT = 0x200,
1102 IRDMA_AEQ_ALIGNMENT = 0x100,
1103 IRDMA_CEQ_ALIGNMENT = 0x100,
1104 IRDMA_CQ0_ALIGNMENT = 0x100,
1105 IRDMA_SD_BUF_ALIGNMENT = 0x80,
1106 IRDMA_FEATURE_BUF_ALIGNMENT = 0x8,
1110 ICRDMA_ANY_PROTOCOL = 0,
1116 * set_64bit_val - set 64 bit value to hw wqe
1127 * set_32bit_val - set 32 bit value to hw wqe
1138 * get_64bit_val - read 64 bit value from wqe
1149 * get_32bit_val - read 32 bit value from wqe