6567 	struct hns_roce_eq_context *eqc;  in config_eqc()  local
6571 	eqc = mb_buf;  in config_eqc()
6572 	memset(eqc, 0, sizeof(struct hns_roce_eq_context));  in config_eqc()
6586 	hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);  in config_eqc()
6587 	hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);  in config_eqc()
6588 	hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);  in config_eqc()
6589 	hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);  in config_eqc()
6590 	hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);  in config_eqc()
6591 	hr_reg_write(eqc, EQC_EQN, eq->eqn);  in config_eqc()
6592 	hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);  in config_eqc()
6593 	hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,  in config_eqc()
6595 	hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,  in config_eqc()
6597 	hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);  in config_eqc()
6598 	hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);  in config_eqc()
6609 	hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);  in config_eqc()
6610 	hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);  in config_eqc()
6611 	hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);  in config_eqc()
6612 	hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);  in config_eqc()
6613 	hr_reg_write(eqc, EQC_SHIFT, eq->shift);  in config_eqc()
6614 	hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);  in config_eqc()
6615 	hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);  in config_eqc()
6616 	hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);  in config_eqc()
6617 	hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);  in config_eqc()
6618 	hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);  in config_eqc()
6619 	hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);  in config_eqc()
6620 	hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);  in config_eqc()
6621 	hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);  in config_eqc()