Lines Matching +full:tx +full:- +full:swing +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
90 * fields required to re-initialize after a chip reset, or for
111 return -EINVAL; in hfi1_pcie_ddinit()
114 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
115 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
117 return -ENOMEM; in hfi1_pcie_ddinit()
119 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
122 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
123 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
128 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
130 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
132 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
133 addr + dd->base2_start, in hfi1_pcie_ddinit()
134 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
135 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
139 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
140 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
142 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
143 if (!dd->piobase) { in hfi1_pcie_ddinit()
147 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
149 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
152 * Map the chip's RcvArray as write-combining to allow us in hfi1_pcie_ddinit()
155 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
157 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
162 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
164 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
167 ret = -ENOMEM; in hfi1_pcie_ddinit()
173 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
179 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
180 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
181 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
182 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
183 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
184 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
185 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
186 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
187 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
188 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
189 if (dd->piobase) in hfi1_pcie_ddcleanup()
190 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
191 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
214 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
220 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
226 dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); in update_lbus_info()
227 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
228 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
229 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
239 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
242 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
244 return -EINVAL; in pcie_speeds()
248 dd->link_gen3_capable = 1; in pcie_speeds()
250 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
260 dd->link_gen3_capable = 0; in pcie_speeds()
264 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed in pcie_speeds()
267 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
268 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
270 dd->link_gen3_capable = 0; in pcie_speeds()
276 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
290 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
294 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
295 dd->pcibar0); in restore_pci_variables()
299 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
300 dd->pcibar1); in restore_pci_variables()
304 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
308 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
309 dd->pcie_devctl); in restore_pci_variables()
313 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
314 dd->pcie_lnkctl); in restore_pci_variables()
318 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
319 dd->pcie_devctl2); in restore_pci_variables()
323 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
327 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
328 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
329 dd->pci_tph2); in restore_pci_variables()
349 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
350 &dd->pcibar0); in save_pci_variables()
354 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
355 &dd->pcibar1); in save_pci_variables()
359 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
363 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
367 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
368 &dd->pcie_devctl); in save_pci_variables()
372 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
373 &dd->pcie_lnkctl); in save_pci_variables()
377 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
378 &dd->pcie_devctl2); in save_pci_variables()
382 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
386 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
387 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
388 &dd->pci_tph2); in save_pci_variables()
400 * BIOS may not set PCIe bus-utilization parameters for best performance.
408 * tune_pcie_caps() - Code to adjust PCIe capabilities.
423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
427 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
433 parent = dd->pcidev->bus->self; in tune_pcie_caps()
442 if (!pci_is_root_bus(parent->bus)) { in tune_pcie_caps()
450 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
454 rc_mpss = parent->pcie_mpss; in tune_pcie_caps()
455 rc_mps = ffs(pcie_get_mps(parent)) - 8; in tune_pcie_caps()
457 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
458 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
475 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
481 * which is code '5' (log2(4096) - 7) in tune_pcie_caps()
489 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
497 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
528 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
550 if (dd && dd->pport) { in pci_mmio_enabled()
551 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
578 * unlike sysfs-requested reset. Better than in pci_resume()
581 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
619 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
634 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
638 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/…
721 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
733 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); in load_eq_table()
738 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
762 return -EINVAL; in load_eq_table()
784 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
799 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
803 if (!dev->bus->self) { in trigger_sbr()
805 return -ENOTTY; in trigger_sbr()
809 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in trigger_sbr()
814 return -ENOTTY; in trigger_sbr()
822 return pci_bridge_secondary_bus_reset(dev->bus->self); in trigger_sbr()
843 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
845 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
872 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
885 * For Discrete, use full-swing. in write_xmt_margin()
886 * - PCIe TX defaults to full-swing. in write_xmt_margin()
888 * For Integrated, use half-swing in write_xmt_margin()
889 * - Copy xmt_margin and xmt_margin_oe in write_xmt_margin()
892 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
937 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
957 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
970 /* off or invalid target - skip */ in do_pcie_gen3_transition()
976 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
979 pcie_force ? "re-doing anyway" : "skipping"); in do_pcie_gen3_transition()
995 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1005 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1007 ret = -ENOSYS; in do_pcie_gen3_transition()
1045 * PcieCfgSpcie1 - Link Control 3 in do_pcie_gen3_transition()
1046 * Leave at reset value. No need to set PerfEq - link equalization in do_pcie_gen3_transition()
1051 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ in do_pcie_gen3_transition()
1052 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1057 * PcieCfgRegPl2 - Port Force Link in do_pcie_gen3_transition()
1059 * Set the low power field to 0x10 to avoid unnecessary power in do_pcie_gen3_transition()
1063 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1066 * PcieCfgRegPl100 - Gen3 Control in do_pcie_gen3_transition()
1073 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1076 * PcieCfgRegPl101 - Gen3 EQ FS and LF in do_pcie_gen3_transition()
1077 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping in do_pcie_gen3_transition()
1078 * PcieCfgRegPl103 - Gen3 EQ Preset Index in do_pcie_gen3_transition()
1079 * PcieCfgRegPl105 - Gen3 EQ Status in do_pcie_gen3_transition()
1083 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1091 /* bit 0 - discrete on/off */ in do_pcie_gen3_transition()
1101 /* bit 1 - integrated on/off */ in do_pcie_gen3_transition()
1104 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1114 * PcieCfgRegPl106 - Gen3 EQ Control in do_pcie_gen3_transition()
1120 if (pset > 10) { /* valid range is 0-10, inclusive */ in do_pcie_gen3_transition()
1126 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1223 ret = pcie_capability_clear_and_set_word(dd->pcidev, PCI_EXP_LNKCTL2, in do_pcie_gen3_transition()
1263 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1274 ret = -EIO; in do_pcie_gen3_transition()
1298 * the SBR. Then check for any per-lane errors. Then look over in do_pcie_gen3_transition()
1304 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1306 ret = -ENOSYS; in do_pcie_gen3_transition()
1316 /* check for any per-lane errors */ in do_pcie_gen3_transition()
1317 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1324 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1329 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1332 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1333 ret = -EIO; in do_pcie_gen3_transition()
1342 ret = -EIO; in do_pcie_gen3_transition()
1349 dd->lbus_info); in do_pcie_gen3_transition()
1351 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1352 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1362 ret = -EIO; in do_pcie_gen3_transition()
1369 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()