1365 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);  in read_write_csr()
1469 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);  in dc_access_lcb_cntr()
1519 	hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);  in read_write_sw()
12207 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_cntrs()
12210 				hfi1_cdbg(CNTR, "\tDisabled");  in hfi1_read_cntrs()
12213 					hfi1_cdbg(CNTR, "\tPer VL");  in hfi1_read_cntrs()
12220 						   CNTR,  in hfi1_read_cntrs()
12227 					hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12234 						hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12245 					hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_cntrs()
12273 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_portcntrs()
12276 				hfi1_cdbg(CNTR, "\tDisabled");  in hfi1_read_portcntrs()
12281 				hfi1_cdbg(CNTR, "\tPer VL");  in hfi1_read_portcntrs()
12287 					   CNTR,  in hfi1_read_portcntrs()
12298 				hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_portcntrs()
12351 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in read_dev_port_cntr()
12386 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in read_dev_port_cntr()
12402 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in write_dev_port_cntr()
12420 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in write_dev_port_cntr()
12518 	    CNTR,  in do_update_synth_timer()
12528 		hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",  in do_update_synth_timer()
12532 		hfi1_cdbg(CNTR,  in do_update_synth_timer()
12536 			hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",  in do_update_synth_timer()
12543 		hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);  in do_update_synth_timer()
12580 		hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",  in do_update_synth_timer()
12584 		hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);  in do_update_synth_timer()