Lines Matching +full:gated +full:- +full:fixed +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/iio/timer/stm32-timer-trigger.h>
14 #include <linux/mfd/stm32-timers.h>
129 /* Period and prescaler values depends of clock rate */ in stm32_timer_start()
130 div = (unsigned long long)clk_get_rate(priv->clk); in stm32_timer_start()
140 while (div > priv->max_arr) { in stm32_timer_start()
148 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); in stm32_timer_start()
149 return -EINVAL; in stm32_timer_start()
153 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_start()
155 return -EBUSY; in stm32_timer_start()
157 guard(mutex)(&priv->lock); in stm32_timer_start()
158 if (!priv->enabled) { in stm32_timer_start()
159 priv->enabled = true; in stm32_timer_start()
160 ret = clk_enable(priv->clk); in stm32_timer_start()
165 regmap_write(priv->regmap, TIM_PSC, prescaler); in stm32_timer_start()
166 regmap_write(priv->regmap, TIM_ARR, prd - 1); in stm32_timer_start()
167 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_timer_start()
170 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_timer_start()
171 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, in stm32_timer_start()
174 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, in stm32_timer_start()
178 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_timer_start()
181 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_timer_start()
191 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_stop()
195 mutex_lock(&priv->lock); in stm32_timer_stop()
197 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_timer_stop()
198 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_timer_stop()
199 regmap_write(priv->regmap, TIM_PSC, 0); in stm32_timer_stop()
200 regmap_write(priv->regmap, TIM_ARR, 0); in stm32_timer_stop()
203 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_timer_stop()
204 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); in stm32_timer_stop()
206 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS); in stm32_timer_stop()
209 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_timer_stop()
211 if (priv->enabled) { in stm32_timer_stop()
212 priv->enabled = false; in stm32_timer_stop()
213 clk_disable(priv->clk); in stm32_timer_stop()
215 mutex_unlock(&priv->lock); in stm32_timer_stop()
250 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_tt_read_frequency()
251 regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_tt_read_frequency()
252 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_tt_read_frequency()
255 freq = (unsigned long long)clk_get_rate(priv->clk); in stm32_tt_read_frequency()
298 regmap_read(priv->regmap, TIM_CR2, &cr2); in stm32_tt_show_master_mode()
300 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_tt_show_master_mode()
317 if (stm32_timer_is_trgo2_name(trig->name)) { in stm32_tt_store_master_mode()
330 guard(mutex)(&priv->lock); in stm32_tt_store_master_mode()
331 if (!priv->enabled) { in stm32_tt_store_master_mode()
332 /* Clock should be enabled first */ in stm32_tt_store_master_mode()
333 priv->enabled = true; in stm32_tt_store_master_mode()
334 ret = clk_enable(priv->clk); in stm32_tt_store_master_mode()
338 regmap_update_bits(priv->regmap, TIM_CR2, mask, in stm32_tt_store_master_mode()
344 return -EINVAL; in stm32_tt_store_master_mode()
355 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_tt_show_master_mode_avail()
361 len += scnprintf(buf + len, PAGE_SIZE - len, in stm32_tt_show_master_mode_avail()
365 buf[len - 1] = '\n'; in stm32_tt_show_master_mode_avail()
401 list_for_each_entry(tr, &priv->tr_list, alloc_list) in stm32_unregister_iio_triggers()
408 const char * const *cur = priv->triggers; in stm32_register_iio_triggers()
410 INIT_LIST_HEAD(&priv->tr_list); in stm32_register_iio_triggers()
417 if (cur_is_trgo2 && !priv->has_trgo2) { in stm32_register_iio_triggers()
422 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); in stm32_register_iio_triggers()
424 return -ENOMEM; in stm32_register_iio_triggers()
426 trig->dev.parent = priv->dev->parent; in stm32_register_iio_triggers()
427 trig->ops = &timer_trigger_ops; in stm32_register_iio_triggers()
434 trig->dev.groups = stm32_trigger_attr_groups; in stm32_register_iio_triggers()
444 list_add_tail(&trig->alloc_list, &priv->tr_list); in stm32_register_iio_triggers()
460 regmap_read(priv->regmap, TIM_CNT, &dat); in stm32_counter_read_raw()
465 regmap_read(priv->regmap, TIM_CR1, &dat); in stm32_counter_read_raw()
470 regmap_read(priv->regmap, TIM_SMCR, &dat); in stm32_counter_read_raw()
483 return -EINVAL; in stm32_counter_read_raw()
495 return regmap_write(priv->regmap, TIM_CNT, val); in stm32_counter_write_raw()
498 /* fixed scale */ in stm32_counter_write_raw()
499 return -EINVAL; in stm32_counter_write_raw()
502 guard(mutex)(&priv->lock); in stm32_counter_write_raw()
504 if (!priv->enabled) { in stm32_counter_write_raw()
505 priv->enabled = true; in stm32_counter_write_raw()
506 ret = clk_enable(priv->clk); in stm32_counter_write_raw()
510 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_counter_write_raw()
512 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_counter_write_raw()
513 if (priv->enabled) { in stm32_counter_write_raw()
514 priv->enabled = false; in stm32_counter_write_raw()
515 clk_disable(priv->clk); in stm32_counter_write_raw()
522 return -EINVAL; in stm32_counter_write_raw()
530 const char * const *cur = priv->valids; in stm32_counter_validate_trigger()
534 return -EINVAL; in stm32_counter_validate_trigger()
537 if (!strncmp(trig->name, *cur, strlen(trig->name))) { in stm32_counter_validate_trigger()
538 regmap_update_bits(priv->regmap, in stm32_counter_validate_trigger()
547 return -EINVAL; in stm32_counter_validate_trigger()
566 regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS); in stm32_set_trigger_mode()
577 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_get_trigger_mode()
579 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; in stm32_get_trigger_mode()
591 "gated",
606 return -EINVAL; in stm32_enable_mode2sms()
621 * enable counter clock, so it can use it. Keeps it in sync with CEN. in stm32_set_enable_mode()
623 scoped_guard(mutex, &priv->lock) { in stm32_set_enable_mode()
624 if (sms == 6 && !priv->enabled) { in stm32_set_enable_mode()
625 ret = clk_enable(priv->clk); in stm32_set_enable_mode()
629 priv->enabled = true; in stm32_set_enable_mode()
633 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); in stm32_set_enable_mode()
649 return -EINVAL; in stm32_sms2enable_mode()
658 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_get_enable_mode()
679 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_count_get_preset()
698 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_count_set_preset()
699 regmap_write(priv->regmap, TIM_ARR, preset); in stm32_count_set_preset()
738 indio_dev->name = dev_name(dev); in stm32_setup_counter_device()
739 indio_dev->info = &stm32_trigger_info; in stm32_setup_counter_device()
740 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; in stm32_setup_counter_device()
741 indio_dev->num_channels = 1; in stm32_setup_counter_device()
742 indio_dev->channels = &stm32_trigger_channel; in stm32_setup_counter_device()
760 return (trig->ops == &timer_trigger_ops); in is_stm32_timer_trigger()
772 regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); in stm32_timer_detect_trgo2()
773 regmap_read(priv->regmap, TIM_CR2, &val); in stm32_timer_detect_trgo2()
774 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); in stm32_timer_detect_trgo2()
775 priv->has_trgo2 = !!val; in stm32_timer_detect_trgo2()
780 struct device *dev = &pdev->dev; in stm32_timer_trigger_probe()
782 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); in stm32_timer_trigger_probe()
794 index >= cfg->num_valids_table) in stm32_timer_trigger_probe()
795 return -EINVAL; in stm32_timer_trigger_probe()
798 if (cfg->valids_table && *cfg->valids_table[index]) in stm32_timer_trigger_probe()
804 return -ENOMEM; in stm32_timer_trigger_probe()
806 priv->dev = dev; in stm32_timer_trigger_probe()
807 priv->regmap = ddata->regmap; in stm32_timer_trigger_probe()
808 priv->clk = ddata->clk; in stm32_timer_trigger_probe()
809 priv->max_arr = ddata->max_arr; in stm32_timer_trigger_probe()
810 priv->triggers = triggers_table[index]; in stm32_timer_trigger_probe()
811 if (cfg->valids_table && *cfg->valids_table[index]) in stm32_timer_trigger_probe()
812 priv->valids = cfg->valids_table[index]; in stm32_timer_trigger_probe()
814 mutex_init(&priv->lock); in stm32_timer_trigger_probe()
834 regmap_read(priv->regmap, TIM_CCER, &val); in stm32_timer_trigger_remove()
836 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_timer_trigger_remove()
838 if (priv->enabled) in stm32_timer_trigger_remove()
839 clk_disable(priv->clk); in stm32_timer_trigger_remove()
847 if (priv->enabled) { in stm32_timer_trigger_suspend()
849 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); in stm32_timer_trigger_suspend()
850 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2); in stm32_timer_trigger_suspend()
851 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc); in stm32_timer_trigger_suspend()
852 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); in stm32_timer_trigger_suspend()
853 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); in stm32_timer_trigger_suspend()
854 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); in stm32_timer_trigger_suspend()
857 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_timer_trigger_suspend()
858 clk_disable(priv->clk); in stm32_timer_trigger_suspend()
869 if (priv->enabled) { in stm32_timer_trigger_resume()
870 ret = clk_enable(priv->clk); in stm32_timer_trigger_resume()
875 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); in stm32_timer_trigger_resume()
876 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2); in stm32_timer_trigger_resume()
879 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc); in stm32_timer_trigger_resume()
880 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); in stm32_timer_trigger_resume()
881 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); in stm32_timer_trigger_resume()
883 /* Also re-enables the timer */ in stm32_timer_trigger_resume()
884 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); in stm32_timer_trigger_resume()
909 * point to the stm32-timer-cnt driver instead.
916 .compatible = "st,stm32-timer-trigger",
919 .compatible = "st,stm32h7-timer-trigger",
922 .compatible = "st,stm32mp25-timer-trigger",
933 .name = "stm32-timer-trigger",
940 MODULE_ALIAS("platform:stm32-timer-trigger");