Lines Matching +full:5 +full:vout
36 #define D3323AA_REG_BIT_SLAVEA6 5 /* F42. */
76 #define D3323AA_SETTING_END_PATTERN_NR_BITS 5
120 { 5, 1 },
163 /* Input clock or output detection signal (Vout). */
290 "Could not read from GPIO vout-clk (%d)\n", in d3323aa_irq_handler()
330 fsleep((30 + 5) * USEC_PER_MSEC); in d3323aa_reset()
334 * D3323AA_IRQ_RESET_COUNT falling edges on Vout/CLK that it is now in d3323aa_reset()
355 * Vout/CLK signal slowly ramps up during this period. Thus, the digital in d3323aa_reset()
431 "Could not set GPIO vout-clk as input (%d)\n", ret); in d3323aa_setup()
754 devm_gpiod_get(dev, "vout-clk", GPIOD_OUT_LOW); in d3323aa_probe()
757 "Could not get GPIO vout-clk\n"); in d3323aa_probe()