1 // SPDX-License-Identifier: GPL-2.0-only
39  * Register map: anything suffixed *_H is a big-endian high byte and always
76 /* Bits 8-11 select memory bank */
99  * Full Scale (FS)
163  * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
164  * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
184 	if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)  in mpu3050_get_freq()
188 	freq /= (mpu3050->divisor + 1);  in mpu3050_get_freq()
200 	ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,  in mpu3050_start_sampling()
205 	/* Turn on the Z-axis PLL */  in mpu3050_start_sampling()
206 	ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,  in mpu3050_start_sampling()
214 		raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);  in mpu3050_start_sampling()
216 	ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,  in mpu3050_start_sampling()
221 	/* Set low pass filter (sample rate), sync and full scale */  in mpu3050_start_sampling()
222 	ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,  in mpu3050_start_sampling()
224 			   mpu3050->fullscale << MPU3050_FS_SHIFT |  in mpu3050_start_sampling()
225 			   mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);  in mpu3050_start_sampling()
230 	ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);  in mpu3050_start_sampling()
235 	 * Max 50 ms start-up time after setting DLPF_FS_SYNC  in mpu3050_start_sampling()
250 	lpf = mpu3050->lpf;  in mpu3050_set_8khz_samplerate()
251 	divisor = mpu3050->divisor;  in mpu3050_set_8khz_samplerate()
253 	mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */  in mpu3050_set_8khz_samplerate()
254 	mpu3050->divisor = 0; /* Divide by 1 */  in mpu3050_set_8khz_samplerate()
257 	mpu3050->lpf = lpf;  in mpu3050_set_8khz_samplerate()
258 	mpu3050->divisor = divisor;  in mpu3050_set_8khz_samplerate()
274 		switch (chan->type) {  in mpu3050_read_raw()
279 			 * of -30C..85C.  The 23000 includes room temperature  in mpu3050_read_raw()
280 			 * offset of +35C, 280 is the precision scale and x is  in mpu3050_read_raw()
281 			 * the 16-bit signed integer reported by hardware.  in mpu3050_read_raw()
289 			return -EINVAL;  in mpu3050_read_raw()
292 		switch (chan->type) {  in mpu3050_read_raw()
294 			*val = mpu3050->calibration[chan->scan_index-1];  in mpu3050_read_raw()
297 			return -EINVAL;  in mpu3050_read_raw()
303 		switch (chan->type) {  in mpu3050_read_raw()
311 			 * Convert to the corresponding full scale in  in mpu3050_read_raw()
313 			 * span the available scale: to account for the one  in mpu3050_read_raw()
317 			*val = mpu3050_fs_precision[mpu3050->fullscale] * 2;  in mpu3050_read_raw()
321 			return -EINVAL;  in mpu3050_read_raw()
325 		pm_runtime_get_sync(mpu3050->dev);  in mpu3050_read_raw()
326 		mutex_lock(&mpu3050->lock);  in mpu3050_read_raw()
332 		switch (chan->type) {  in mpu3050_read_raw()
334 			ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,  in mpu3050_read_raw()
337 				dev_err(mpu3050->dev,  in mpu3050_read_raw()
347 			ret = regmap_bulk_read(mpu3050->map,  in mpu3050_read_raw()
348 				       MPU3050_AXIS_REGS(chan->scan_index-1),  in mpu3050_read_raw()
352 				dev_err(mpu3050->dev,  in mpu3050_read_raw()
362 			ret = -EINVAL;  in mpu3050_read_raw()
369 	return -EINVAL;  in mpu3050_read_raw()
372 	mutex_unlock(&mpu3050->lock);  in mpu3050_read_raw()
373 	pm_runtime_mark_last_busy(mpu3050->dev);  in mpu3050_read_raw()
374 	pm_runtime_put_autosuspend(mpu3050->dev);  in mpu3050_read_raw()
402 		if (chan->type != IIO_ANGL_VEL)  in mpu3050_write_raw()
403 			return -EINVAL;  in mpu3050_write_raw()
404 		mpu3050->calibration[chan->scan_index-1] = val;  in mpu3050_write_raw()
412 			return -EINVAL;  in mpu3050_write_raw()
419 			mpu3050->lpf = LPF_256_HZ_NOLPF;  in mpu3050_write_raw()
420 			mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;  in mpu3050_write_raw()
424 		mpu3050->lpf = LPF_188_HZ;  in mpu3050_write_raw()
425 		mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;  in mpu3050_write_raw()
428 		if (chan->type != IIO_ANGL_VEL)  in mpu3050_write_raw()
429 			return -EINVAL;  in mpu3050_write_raw()
431 		 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s  in mpu3050_write_raw()
433 		 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35  in mpu3050_write_raw()
434 		 * rad/s. The scale is then for the 16 bits used to cover  in mpu3050_write_raw()
440 			mpu3050->fullscale = FS_2000_DPS;  in mpu3050_write_raw()
451 			mpu3050->fullscale = FS_250_DPS;  in mpu3050_write_raw()
454 			mpu3050->fullscale = FS_500_DPS;  in mpu3050_write_raw()
457 			mpu3050->fullscale = FS_1000_DPS;  in mpu3050_write_raw()
459 			/* Catch-all */  in mpu3050_write_raw()
460 			mpu3050->fullscale = FS_2000_DPS;  in mpu3050_write_raw()
466 	return -EINVAL;  in mpu3050_write_raw()
472 	struct iio_dev *indio_dev = pf->indio_dev;  in mpu3050_trigger_handler()
489 		timestamp = mpu3050->hw_timestamp;  in mpu3050_trigger_handler()
493 	mutex_lock(&mpu3050->lock);  in mpu3050_trigger_handler()
496 	if (mpu3050->hw_irq_trigger) {  in mpu3050_trigger_handler()
503 		ret = regmap_bulk_read(mpu3050->map,  in mpu3050_trigger_handler()
512 			dev_info(mpu3050->dev,  in mpu3050_trigger_handler()
516 			ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,  in mpu3050_trigger_handler()
520 				dev_info(mpu3050->dev, "error resetting FIFO\n");  in mpu3050_trigger_handler()
523 			mpu3050->pending_fifo_footer = false;  in mpu3050_trigger_handler()
527 			dev_dbg(mpu3050->dev,  in mpu3050_trigger_handler()
544 			if (mpu3050->pending_fifo_footer) {  in mpu3050_trigger_handler()
554 			ret = regmap_bulk_read(mpu3050->map,  in mpu3050_trigger_handler()
561 			dev_dbg(mpu3050->dev,  in mpu3050_trigger_handler()
575 			fifocnt -= toread;  in mpu3050_trigger_handler()
577 			mpu3050->pending_fifo_footer = true;  in mpu3050_trigger_handler()
584 				ret = regmap_bulk_read(mpu3050->map,  in mpu3050_trigger_handler()
594 				dev_dbg(mpu3050->dev,  in mpu3050_trigger_handler()
614 	 * - We are using some other trigger (external, like an HRTimer)  in mpu3050_trigger_handler()
619 	 * - The hardware trigger is active but unused and we actually use  in mpu3050_trigger_handler()
625 		dev_dbg(mpu3050->dev,  in mpu3050_trigger_handler()
631 	ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans,  in mpu3050_trigger_handler()
634 		dev_err(mpu3050->dev,  in mpu3050_trigger_handler()
642 	mutex_unlock(&mpu3050->lock);  in mpu3050_trigger_handler()
643 	iio_trigger_notify_done(indio_dev->trig);  in mpu3050_trigger_handler()
652 	pm_runtime_get_sync(mpu3050->dev);  in mpu3050_buffer_preenable()
654 	/* Unless we have OUR trigger active, run at full speed */  in mpu3050_buffer_preenable()
655 	if (!mpu3050->hw_irq_trigger)  in mpu3050_buffer_preenable()
665 	pm_runtime_mark_last_busy(mpu3050->dev);  in mpu3050_buffer_postdisable()
666 	pm_runtime_put_autosuspend(mpu3050->dev);  in mpu3050_buffer_postdisable()
682 	return &mpu3050->orientation;  in mpu3050_get_mount_matrix()
735  * calculations done with fractions in the scale raw get/set functions.
759  * mpu3050_read_mem() - read MPU-3050 internal memory
774 	ret = regmap_write(mpu3050->map,  in mpu3050_read_mem()
780 	ret = regmap_write(mpu3050->map,  in mpu3050_read_mem()
786 	return regmap_bulk_read(mpu3050->map,  in mpu3050_read_mem()
799 	ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,  in mpu3050_hw_init()
805 	ret = regmap_update_bits(mpu3050->map,  in mpu3050_hw_init()
813 	ret = regmap_write(mpu3050->map,  in mpu3050_hw_init()
819 	/* Read out the 8 bytes of OTP (one-time-programmable) memory */  in mpu3050_hw_init()
830 	/* This is device-unique data so it goes into the entropy pool */  in mpu3050_hw_init()
835 	dev_info(mpu3050->dev,  in mpu3050_hw_init()
838 		 /* Die ID, bits 0-12 */  in mpu3050_hw_init()
840 		 /* Wafer ID, bits 13-17 */  in mpu3050_hw_init()
842 		 /* A lot ID, bits 18-33 */  in mpu3050_hw_init()
844 		 /* W lot ID, bits 34-45 */  in mpu3050_hw_init()
846 		 /* WP ID, bits 47-49 */  in mpu3050_hw_init()
848 		 /* rev ID, bits 50-55 */  in mpu3050_hw_init()
858 	ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);  in mpu3050_power_up()
860 		dev_err(mpu3050->dev, "cannot enable regulators\n");  in mpu3050_power_up()
864 	 * 20-100 ms start-up time for register read/write according to  in mpu3050_power_up()
870 	ret = regmap_clear_bits(mpu3050->map, MPU3050_PWR_MGM,  in mpu3050_power_up()
873 		regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);  in mpu3050_power_up()
874 		dev_err(mpu3050->dev, "error setting power mode\n");  in mpu3050_power_up()
887 	 * Put MPU-3050 into sleep mode before cutting regulators.  in mpu3050_power_down()
893 	ret = regmap_set_bits(mpu3050->map, MPU3050_PWR_MGM,  in mpu3050_power_down()
896 		dev_err(mpu3050->dev, "error putting to sleep\n");  in mpu3050_power_down()
898 	ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);  in mpu3050_power_down()
900 		dev_err(mpu3050->dev, "error disabling regulators\n");  in mpu3050_power_down()
911 	if (!mpu3050->hw_irq_trigger)  in mpu3050_irq_handler()
915 	mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);  in mpu3050_irq_handler()
929 	ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);  in mpu3050_irq_thread()
931 		dev_err(mpu3050->dev, "error reading IRQ status\n");  in mpu3050_irq_thread()
943  * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
958 		ret = regmap_write(mpu3050->map,  in mpu3050_drdy_trigger_set_state()
962 			dev_err(mpu3050->dev, "error disabling IRQ\n");  in mpu3050_drdy_trigger_set_state()
965 		ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);  in mpu3050_drdy_trigger_set_state()
967 			dev_err(mpu3050->dev, "error clearing IRQ status\n");  in mpu3050_drdy_trigger_set_state()
970 		ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);  in mpu3050_drdy_trigger_set_state()
972 			dev_err(mpu3050->dev, "error disabling FIFO\n");  in mpu3050_drdy_trigger_set_state()
974 		ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,  in mpu3050_drdy_trigger_set_state()
977 			dev_err(mpu3050->dev, "error resetting FIFO\n");  in mpu3050_drdy_trigger_set_state()
979 		pm_runtime_mark_last_busy(mpu3050->dev);  in mpu3050_drdy_trigger_set_state()
980 		pm_runtime_put_autosuspend(mpu3050->dev);  in mpu3050_drdy_trigger_set_state()
981 		mpu3050->hw_irq_trigger = false;  in mpu3050_drdy_trigger_set_state()
986 		pm_runtime_get_sync(mpu3050->dev);  in mpu3050_drdy_trigger_set_state()
987 		mpu3050->hw_irq_trigger = true;  in mpu3050_drdy_trigger_set_state()
990 		ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);  in mpu3050_drdy_trigger_set_state()
995 		ret = regmap_set_bits(mpu3050->map, MPU3050_USR_CTRL,  in mpu3050_drdy_trigger_set_state()
1001 		mpu3050->pending_fifo_footer = false;  in mpu3050_drdy_trigger_set_state()
1004 		ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,  in mpu3050_drdy_trigger_set_state()
1019 		ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);  in mpu3050_drdy_trigger_set_state()
1021 			dev_err(mpu3050->dev, "error clearing IRQ status\n");  in mpu3050_drdy_trigger_set_state()
1026 		if (mpu3050->irq_actl)  in mpu3050_drdy_trigger_set_state()
1028 		if (mpu3050->irq_latch)  in mpu3050_drdy_trigger_set_state()
1030 		if (mpu3050->irq_opendrain)  in mpu3050_drdy_trigger_set_state()
1033 		ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);  in mpu3050_drdy_trigger_set_state()
1048 	struct device *dev = mpu3050->dev;  in mpu3050_trigger_probe()
1052 	mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,  in mpu3050_trigger_probe()
1053 					       "%s-dev%d",  in mpu3050_trigger_probe()
1054 					       indio_dev->name,  in mpu3050_trigger_probe()
1056 	if (!mpu3050->trig)  in mpu3050_trigger_probe()
1057 		return -ENOMEM;  in mpu3050_trigger_probe()
1060 	mpu3050->irq_opendrain = device_property_read_bool(dev, "drive-open-drain");  in mpu3050_trigger_probe()
1070 		dev_info(&indio_dev->dev,  in mpu3050_trigger_probe()
1074 		mpu3050->irq_actl = true;  in mpu3050_trigger_probe()
1075 		dev_info(&indio_dev->dev,  in mpu3050_trigger_probe()
1079 		mpu3050->irq_latch = true;  in mpu3050_trigger_probe()
1080 		dev_info(&indio_dev->dev,  in mpu3050_trigger_probe()
1090 		mpu3050->irq_latch = true;  in mpu3050_trigger_probe()
1091 		mpu3050->irq_actl = true;  in mpu3050_trigger_probe()
1093 		dev_info(&indio_dev->dev,  in mpu3050_trigger_probe()
1098 		dev_err(&indio_dev->dev,  in mpu3050_trigger_probe()
1106 	if (mpu3050->irq_opendrain)  in mpu3050_trigger_probe()
1113 				   mpu3050->trig->name,  in mpu3050_trigger_probe()
1114 				   mpu3050->trig);  in mpu3050_trigger_probe()
1120 	mpu3050->irq = irq;  in mpu3050_trigger_probe()
1121 	mpu3050->trig->dev.parent = dev;  in mpu3050_trigger_probe()
1122 	mpu3050->trig->ops = &mpu3050_trigger_ops;  in mpu3050_trigger_probe()
1123 	iio_trigger_set_drvdata(mpu3050->trig, indio_dev);  in mpu3050_trigger_probe()
1125 	ret = iio_trigger_register(mpu3050->trig);  in mpu3050_trigger_probe()
1129 	indio_dev->trig = iio_trigger_get(mpu3050->trig);  in mpu3050_trigger_probe()
1146 		return -ENOMEM;  in mpu3050_common_probe()
1149 	mpu3050->dev = dev;  in mpu3050_common_probe()
1150 	mpu3050->map = map;  in mpu3050_common_probe()
1151 	mutex_init(&mpu3050->lock);  in mpu3050_common_probe()
1153 	mpu3050->fullscale = FS_2000_DPS;  in mpu3050_common_probe()
1155 	mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;  in mpu3050_common_probe()
1156 	mpu3050->divisor = 99;  in mpu3050_common_probe()
1159 	ret = iio_read_mount_matrix(dev, &mpu3050->orientation);  in mpu3050_common_probe()
1164 	mpu3050->regs[0].supply = mpu3050_reg_vdd;  in mpu3050_common_probe()
1165 	mpu3050->regs[1].supply = mpu3050_reg_vlogic;  in mpu3050_common_probe()
1166 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),  in mpu3050_common_probe()
1167 				      mpu3050->regs);  in mpu3050_common_probe()
1180 		ret = -ENODEV;  in mpu3050_common_probe()
1188 		ret = -ENODEV;  in mpu3050_common_probe()
1195 		ret = -ENODEV;  in mpu3050_common_probe()
1199 	dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",  in mpu3050_common_probe()
1206 	indio_dev->channels = mpu3050_channels;  in mpu3050_common_probe()
1207 	indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);  in mpu3050_common_probe()
1208 	indio_dev->info = &mpu3050_info;  in mpu3050_common_probe()
1209 	indio_dev->available_scan_masks = mpu3050_scan_masks;  in mpu3050_common_probe()
1210 	indio_dev->modes = INDIO_DIRECT_MODE;  in mpu3050_common_probe()
1211 	indio_dev->name = name;  in mpu3050_common_probe()
1242 	 * start-up time. 100ms start-up time means 10000ms autosuspend,  in mpu3050_common_probe()
1268 	if (mpu3050->irq)  in mpu3050_common_remove()
1269 		free_irq(mpu3050->irq, mpu3050);  in mpu3050_common_remove()