1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
132 		return regmap_read(st->regmap, reg, readval);  in admv4420_reg_access()
134 		return regmap_write(st->regmap, reg, writeval);  in admv4420_reg_access()
142 	put_unaligned_le32(frac_val, st->transf_buf);  in admv4420_set_n_counter()
143 	ret = regmap_bulk_write(st->regmap, ADMV4420_FRAC_L, st->transf_buf, 3);  in admv4420_set_n_counter()
147 	put_unaligned_le32(mod_val, st->transf_buf);  in admv4420_set_n_counter()
148 	ret = regmap_bulk_write(st->regmap, ADMV4420_MOD_L, st->transf_buf, 3);  in admv4420_set_n_counter()
152 	put_unaligned_le32(int_val, st->transf_buf);  in admv4420_set_n_counter()
153 	return regmap_bulk_write(st->regmap, ADMV4420_INT_L, st->transf_buf, 2);  in admv4420_set_n_counter()
165 		*val = div_u64_rem(st->lo_freq_hz, MICRO, val2);  in admv4420_read_raw()
169 		return -EINVAL;  in admv4420_read_raw()
190 	struct device *dev = &st->spi->dev;  in admv4420_fw_parse()
194 	ret = device_property_read_u32(dev, "adi,lo-freq-khz", &tmp);  in admv4420_fw_parse()
196 		st->lo_freq_hz = (u64)tmp * KILO;  in admv4420_fw_parse()
198 	st->ref_block.ref_single_ended = device_property_read_bool(dev,  in admv4420_fw_parse()
199 								   "adi,ref-ext-single-ended-en");  in admv4420_fw_parse()
204 	return div_u64(st->vco_freq_hz * 10, st->n_counter.n_counter);  in admv4420_calc_pfd_vco()
212 	doubler = st->ref_block.doubler_en ? 2 : 1;  in admv4420_calc_pfd_ref()
213 	divide_by_2 = st->ref_block.divide_by_2_en ? 2 : 1;  in admv4420_calc_pfd_ref()
216 	return (tmp / (st->ref_block.divider * divide_by_2));  in admv4420_calc_pfd_ref()
224 	st->ref_block.doubler_en = false;  in admv4420_calc_parameters()
225 	st->ref_block.divide_by_2_en = false;  in admv4420_calc_parameters()
226 	st->vco_freq_hz = div_u64(st->lo_freq_hz, 2);  in admv4420_calc_parameters()
228 	for (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER;  in admv4420_calc_parameters()
229 	    st->ref_block.divider++) {  in admv4420_calc_parameters()
231 		for (st->n_counter.n_counter = 1; st->n_counter.n_counter < MAX_N_COUNTER;  in admv4420_calc_parameters()
232 		    st->n_counter.n_counter++) {  in admv4420_calc_parameters()
243 		st->n_counter.n_counter = 1;  in admv4420_calc_parameters()
246 		return -1;  in admv4420_calc_parameters()
248 	st->n_counter.int_val = div_u64_rem(st->n_counter.n_counter, 10, &st->n_counter.frac_val);  in admv4420_calc_parameters()
249 	st->n_counter.mod_val = 10;  in admv4420_calc_parameters()
257 	struct device *dev = indio_dev->dev.parent;  in admv4420_setup()
261 	ret = regmap_write(st->regmap, ADMV4420_SPI_CONFIG_1,  in admv4420_setup()
266 	ret = regmap_write(st->regmap, ADMV4420_SPI_CONFIG_1,  in admv4420_setup()
272 	ret = regmap_write(st->regmap,  in admv4420_setup()
278 	ret = regmap_read(st->regmap, ADMV4420_SCRATCHPAD, &val);  in admv4420_setup()
284 		return -EIO;  in admv4420_setup()
287 	ret = regmap_write(st->regmap,  in admv4420_setup()
293 	ret = regmap_read(st->regmap, ADMV4420_SCRATCHPAD, &val);  in admv4420_setup()
299 		return -EIO;  in admv4420_setup()
302 	st->mux_sel = ADMV4420_LOCK_DTCT;  in admv4420_setup()
303 	st->lo_freq_hz = ADMV4420_DEFAULT_LO_FREQ_HZ;  in admv4420_setup()
309 		dev_err(dev, "Failed calc parameters for %lld ", st->vco_freq_hz);  in admv4420_setup()
313 	ret = regmap_write(st->regmap, ADMV4420_R_DIV_L,  in admv4420_setup()
314 			   FIELD_GET(0xFF, st->ref_block.divider));  in admv4420_setup()
318 	ret = regmap_write(st->regmap, ADMV4420_R_DIV_H,  in admv4420_setup()
319 			   FIELD_GET(0xFF00, st->ref_block.divider));  in admv4420_setup()
323 	ret = regmap_write(st->regmap, ADMV4420_REFERENCE,  in admv4420_setup()
324 			   st->ref_block.divide_by_2_en |  in admv4420_setup()
325 			   FIELD_PREP(ADMV4420_REFERENCE_MODE_MASK, st->ref_block.ref_single_ended) |  in admv4420_setup()
326 			   FIELD_PREP(ADMV4420_REFERENCE_DOUBLER_MASK, st->ref_block.doubler_en));  in admv4420_setup()
330 	ret = admv4420_set_n_counter(st, st->n_counter.int_val,  in admv4420_setup()
331 				     st->n_counter.frac_val,  in admv4420_setup()
332 				     st->n_counter.mod_val);  in admv4420_setup()
336 	ret = regmap_write(st->regmap, ADMV4420_PLL_MUX_SEL, st->mux_sel);  in admv4420_setup()
340 	return regmap_write(st->regmap, ADMV4420_ENABLES,  in admv4420_setup()
352 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));  in admv4420_probe()
354 		return -ENOMEM;  in admv4420_probe()
358 		return dev_err_probe(&spi->dev, PTR_ERR(regmap),  in admv4420_probe()
362 	st->spi = spi;  in admv4420_probe()
363 	st->regmap = regmap;  in admv4420_probe()
365 	indio_dev->name = "admv4420";  in admv4420_probe()
366 	indio_dev->info = &admv4420_info;  in admv4420_probe()
367 	indio_dev->channels = admv4420_channels;  in admv4420_probe()
368 	indio_dev->num_channels = ARRAY_SIZE(admv4420_channels);  in admv4420_probe()
372 		dev_err(&spi->dev, "Setup ADMV4420 failed (%d)\n", ret);  in admv4420_probe()
376 	return devm_iio_device_register(&spi->dev, indio_dev);  in admv4420_probe()