Lines Matching +full:phase +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
8 #include <linux/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
127 guard(mutex)(&st->lock); in axi_dac_enable()
128 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
133 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all in axi_dac_enable()
137 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
144 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
152 guard(mutex)(&st->lock); in axi_dac_disable()
153 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); in axi_dac_disable()
162 if (device_property_read_string(st->dev, "dma-names", &dma_name)) in axi_dac_request_buffer()
165 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, in axi_dac_request_buffer()
191 return -EINVAL; in __axi_dac_frequency_get()
193 if (!st->dac_clk) { in __axi_dac_frequency_get()
194 dev_err(st->dev, "Sampling rate is 0...\n"); in __axi_dac_frequency_get()
195 return -EINVAL; in __axi_dac_frequency_get()
203 ret = regmap_read(st->regmap, reg, &raw); in __axi_dac_frequency_get()
208 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); in __axi_dac_frequency_get()
220 scoped_guard(mutex, &st->lock) { in axi_dac_frequency_get()
221 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); in axi_dac_frequency_get()
237 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) in axi_dac_scale_get()
238 return -EINVAL; in axi_dac_scale_get()
241 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); in axi_dac_scale_get()
243 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); in axi_dac_scale_get()
245 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_scale_get()
258 vals[0] *= -1; in axi_dac_scale_get()
260 vals[1] *= -1; in axi_dac_scale_get()
271 u32 reg, raw, phase; in axi_dac_phase_get() local
274 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) in axi_dac_phase_get()
275 return -EINVAL; in axi_dac_phase_get()
278 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); in axi_dac_phase_get()
280 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); in axi_dac_phase_get()
282 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_phase_get()
287 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); in axi_dac_phase_get()
289 vals[0] = phase / MEGA; in axi_dac_phase_get()
290 vals[1] = phase % MEGA; in axi_dac_phase_get()
305 return -EINVAL; in __axi_dac_frequency_set()
308 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", in __axi_dac_frequency_set()
310 return -EINVAL; in __axi_dac_frequency_set()
320 ret = regmap_update_bits(st->regmap, reg, in __axi_dac_frequency_set()
326 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in __axi_dac_frequency_set()
341 guard(mutex)(&st->lock); in axi_dac_frequency_set()
342 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, in axi_dac_frequency_set()
358 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) in axi_dac_scale_set()
359 return -EINVAL; in axi_dac_scale_set()
366 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) in axi_dac_scale_set()
367 return -EINVAL; in axi_dac_scale_set()
372 scale *= -1; in axi_dac_scale_set()
378 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); in axi_dac_scale_set()
380 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); in axi_dac_scale_set()
382 guard(mutex)(&st->lock); in axi_dac_scale_set()
383 ret = regmap_write(st->regmap, reg, raw); in axi_dac_scale_set()
388 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in axi_dac_scale_set()
400 int integer, frac, phase; in axi_dac_phase_set() local
404 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX) in axi_dac_phase_set()
405 return -EINVAL; in axi_dac_phase_set()
411 phase = integer * MEGA + frac; in axi_dac_phase_set()
412 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) in axi_dac_phase_set()
413 return -EINVAL; in axi_dac_phase_set()
415 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); in axi_dac_phase_set()
418 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); in axi_dac_phase_set()
420 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); in axi_dac_phase_set()
422 guard(mutex)(&st->lock); in axi_dac_phase_set()
423 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, in axi_dac_phase_set()
429 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in axi_dac_phase_set()
457 return -EOPNOTSUPP; in axi_dac_ext_info_set()
470 private - AXI_DAC_FREQ_TONE_1); in axi_dac_ext_info_get()
474 private - AXI_DAC_SCALE_TONE_1); in axi_dac_ext_info_get()
478 private - AXI_DAC_PHASE_TONE_1); in axi_dac_ext_info_get()
480 return -EOPNOTSUPP; in axi_dac_ext_info_get()
499 if (chan->type != IIO_ALTVOLTAGE) in axi_dac_extend_chan()
500 return -EINVAL; in axi_dac_extend_chan()
501 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) in axi_dac_extend_chan()
505 chan->ext_info = axi_dac_ext_info; in axi_dac_extend_chan()
516 return -EINVAL; in axi_dac_data_source_set()
520 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
525 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
530 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
535 return -EINVAL; in axi_dac_data_source_set()
547 return -EINVAL; in axi_dac_data_source_get()
549 ret = regmap_read(st->regmap, AXI_DAC_CHAN_CNTRL_7_REG(chan), &val); in axi_dac_data_source_get()
564 return -EIO; in axi_dac_data_source_get()
576 return -EINVAL; in axi_dac_set_sample_rate()
578 return -EINVAL; in axi_dac_set_sample_rate()
579 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) in axi_dac_set_sample_rate()
583 guard(mutex)(&st->lock); in axi_dac_set_sample_rate()
591 if (!st->dac_clk) { in axi_dac_set_sample_rate()
592 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
606 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
617 return regmap_read(st->regmap, reg, readval); in axi_dac_reg_access()
619 return regmap_write(st->regmap, reg, writeval); in axi_dac_reg_access()
626 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_ddr_enable()
634 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_ddr_disable()
643 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, val, in axi_dac_wait_bus_free()
646 if (ret == -ETIMEDOUT) in axi_dac_wait_bus_free()
647 dev_err(st->dev, "AXI bus timeout\n"); in axi_dac_wait_bus_free()
661 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_stream_enable()
669 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_stream_disable()
678 return -EINVAL; in axi_dac_data_transfer_addr()
684 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_transfer_addr()
695 switch (data->type) { in axi_dac_data_format_set()
697 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_data_format_set()
700 return -EINVAL; in axi_dac_data_format_set()
723 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival); in __axi_dac_bus_reg_write()
728 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in __axi_dac_bus_reg_write()
731 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in __axi_dac_bus_reg_write()
736 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
742 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
753 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
762 guard(mutex)(&st->lock); in axi_dac_bus_reg_write()
772 guard(mutex)(&st->lock); in axi_dac_bus_reg_read()
787 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); in axi_dac_bus_reg_read()
797 return -EINVAL; in axi_dac_bus_set_io_mode()
799 guard(mutex)(&st->lock); in axi_dac_bus_set_io_mode()
801 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_bus_set_io_mode()
822 .bus_sample_data_clock_hz = st->dac_clk_rate, in axi_dac_create_platform_device()
825 .parent = st->dev, in axi_dac_create_platform_device()
838 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev); in axi_dac_create_platform_device()
870 .name = "axi-dac",
875 .name = "axi-ad3552r",
894 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); in axi_dac_probe()
896 return -ENOMEM; in axi_dac_probe()
898 st->info = device_get_match_data(&pdev->dev); in axi_dac_probe()
899 if (!st->info) in axi_dac_probe()
900 return -ENODEV; in axi_dac_probe()
901 clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); in axi_dac_probe()
903 /* Backward compat., old fdt versions without clock-names. */ in axi_dac_probe()
904 clk = devm_clk_get_enabled(&pdev->dev, NULL); in axi_dac_probe()
906 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in axi_dac_probe()
910 if (st->info->has_dac_clk) { in axi_dac_probe()
913 dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk"); in axi_dac_probe()
915 return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk), in axi_dac_probe()
919 st->dac_clk_rate = clk_get_rate(dac_clk) / 2; in axi_dac_probe()
926 st->dev = &pdev->dev; in axi_dac_probe()
927 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, in axi_dac_probe()
929 if (IS_ERR(st->regmap)) in axi_dac_probe()
930 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), in axi_dac_probe()
937 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); in axi_dac_probe()
941 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); in axi_dac_probe()
946 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { in axi_dac_probe()
947 dev_err(&pdev->dev, in axi_dac_probe()
949 ADI_AXI_PCORE_VER_MAJOR(st->info->version), in axi_dac_probe()
950 ADI_AXI_PCORE_VER_MINOR(st->info->version), in axi_dac_probe()
951 ADI_AXI_PCORE_VER_PATCH(st->info->version), in axi_dac_probe()
955 return -ENODEV; in axi_dac_probe()
959 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); in axi_dac_probe()
967 * Multiple-Input and Multiple-Output (MIMO). As most of the times we in axi_dac_probe()
971 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_probe()
976 mutex_init(&st->lock); in axi_dac_probe()
978 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st); in axi_dac_probe()
980 return dev_err_probe(&pdev->dev, ret, in axi_dac_probe()
983 device_for_each_child_node_scoped(&pdev->dev, child) { in axi_dac_probe()
986 if (!st->info->has_child_nodes) in axi_dac_probe()
987 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
988 "invalid fdt axi-dac compatible."); in axi_dac_probe()
993 return dev_err_probe(&pdev->dev, ret, in axi_dac_probe()
996 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
1001 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
1005 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", in axi_dac_probe()
1026 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic },
1027 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r },
1034 .name = "adi-axi-dac",