52 	struct iio_backend *back;  member
78 	return st->data->bus_reg_read(st->back, reg, val, xfer_size);  in ad3552r_hs_reg_read()
87 		ret = iio_backend_data_source_set(st->back, i, type);  in ad3552r_hs_set_data_source()
107 	return st->data->bus_reg_write(st->back, reg, rval, xfer_size);  in ad3552r_hs_update_reg_bits()
166 		ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_write_raw()
186 	return st->data->bus_set_io_mode(st->back, bus_mode);  in ad3552r_hs_set_bus_io_mode_hs()
206 	return st->data->bus_reg_write(st->back,  in ad3552r_hs_set_target_io_mode_hs()
265 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_buffer_postenable()
272 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_buffer_postenable()
278 	ret = iio_backend_ddr_enable(st->back);  in ad3552r_hs_buffer_postenable()
301 	ret = iio_backend_data_transfer_addr(st->back, val);  in ad3552r_hs_buffer_postenable()
305 	ret = iio_backend_data_format_set(st->back, 0, &fmt);  in ad3552r_hs_buffer_postenable()
309 	ret = iio_backend_data_stream_enable(st->back);  in ad3552r_hs_buffer_postenable()
317 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER,  in ad3552r_hs_buffer_postenable()
326 	st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);  in ad3552r_hs_buffer_postenable()
329 	iio_backend_ddr_disable(st->back);  in ad3552r_hs_buffer_postenable()
337 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D,  in ad3552r_hs_buffer_postenable()
342 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,  in ad3552r_hs_buffer_postenable()
354 	ret = iio_backend_data_stream_disable(st->back);  in ad3552r_hs_buffer_predisable()
362 	ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);  in ad3552r_hs_buffer_predisable()
371 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_buffer_predisable()
377 	ret = iio_backend_ddr_disable(st->back);  in ad3552r_hs_buffer_predisable()
447 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
452 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
462 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
467 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,  in ad3552r_hs_scratch_pad_test()
485 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch),  in ad3552r_hs_setup_custom_gain()
490 	return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch),  in ad3552r_hs_setup_custom_gain()
510 	return st->data->bus_reg_write(st->back, reg, writeval, 1);  in ad3552r_hs_reg_access()
522 	ret = iio_backend_data_source_get(st->back, 0, &type);  in ad3552r_hs_show_data_source()
622 	ret = iio_backend_ddr_disable(st->back);  in ad3552r_hs_setup()
626 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_setup()
641 	ret = st->data->bus_reg_read(st->back,  in ad3552r_hs_setup()
666 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS,  in ad3552r_hs_setup()
671 	ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_setup()
699 		ret = st->data->bus_reg_write(st->back,  in ad3552r_hs_setup()
821 	st->back = devm_iio_backend_get(&pdev->dev, NULL);  in ad3552r_hs_probe()
822 	if (IS_ERR(st->back))  in ad3552r_hs_probe()
823 		return PTR_ERR(st->back);  in ad3552r_hs_probe()
825 	ret = devm_iio_backend_enable(&pdev->dev, st->back);  in ad3552r_hs_probe()
840 	ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev);  in ad3552r_hs_probe()