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1 // SPDX-License-Identifier: GPL-2.0-only
4 * Digital to Analog converter driver, High Speed version
21 #include "ad3552r-hs.h"
30 * access to both the regions.
32 * Due to the fact that ad3541/2r do not implement QSPI, for proper device
36 * DAC appropriately, together with the backend API to configure the bus mode
39 * Also, important to note that none of the three modes allow to read in DDR.
41 * In non-buffering operations, mode is set to simple SPI SDR for all primary
42 * and secondary region r/w accesses, to avoid to switch the mode each time DAC
43 * register is accessed (raw accesses, r/w), and to be able to dump registers
52 struct iio_backend *back; member
69 [AD3552R_SRC_RAMP_16BIT] = "ramp-16bit",
76 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
78 return st->data->bus_reg_read(st->back, reg, val, xfer_size); in ad3552r_hs_reg_read()
86 for (i = 0; i < st->model_data->num_hw_channels; ++i) { in ad3552r_hs_set_data_source()
87 ret = iio_backend_data_source_set(st->back, i, type); in ad3552r_hs_set_data_source()
107 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); in ad3552r_hs_update_reg_bits()
116 int ch = chan->channel; in ad3552r_hs_read_raw()
126 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * in ad3552r_hs_read_raw()
127 st->model_data->num_spi_data_lanes * 2, in ad3552r_hs_read_raw()
128 chan->scan_type.realbits); in ad3552r_hs_read_raw()
133 /* For RAW accesses, stay always in simple-spi. */ in ad3552r_hs_read_raw()
135 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), in ad3552r_hs_read_raw()
142 *val = st->ch_data[ch].scale_int; in ad3552r_hs_read_raw()
143 *val2 = st->ch_data[ch].scale_dec; in ad3552r_hs_read_raw()
146 *val = st->ch_data[ch].offset_int; in ad3552r_hs_read_raw()
147 *val2 = st->ch_data[ch].offset_dec; in ad3552r_hs_read_raw()
150 return -EINVAL; in ad3552r_hs_read_raw()
164 return -EBUSY; in ad3552r_hs_write_raw()
165 /* For RAW accesses, stay always in simple-spi. */ in ad3552r_hs_write_raw()
166 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_write_raw()
167 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), in ad3552r_hs_write_raw()
173 return -EINVAL; in ad3552r_hs_write_raw()
181 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_bus_io_mode_hs()
186 return st->data->bus_set_io_mode(st->back, bus_mode); in ad3552r_hs_set_bus_io_mode_hs()
197 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_target_io_mode_hs()
203 * Better to not use update here, since generally it is already in ad3552r_hs_set_target_io_mode_hs()
204 * set as DDR mode, and it's not possible to read in DDR mode. in ad3552r_hs_set_target_io_mode_hs()
206 return st->data->bus_reg_write(st->back, in ad3552r_hs_set_target_io_mode_hs()
221 switch (*indio_dev->active_scan_mask) { in ad3552r_hs_buffer_postenable()
223 st->single_channel = true; in ad3552r_hs_buffer_postenable()
228 st->single_channel = true; in ad3552r_hs_buffer_postenable()
233 st->single_channel = false; in ad3552r_hs_buffer_postenable()
238 return -EINVAL; in ad3552r_hs_buffer_postenable()
265 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
271 st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
272 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
274 st->config_d, 1); in ad3552r_hs_buffer_postenable()
278 ret = iio_backend_ddr_enable(st->back); in ad3552r_hs_buffer_postenable()
287 /* Set target to best high speed mode (D or QSPI). */ in ad3552r_hs_buffer_postenable()
292 /* Set bus to best high speed mode (D or QSPI). */ in ad3552r_hs_buffer_postenable()
301 ret = iio_backend_data_transfer_addr(st->back, val); in ad3552r_hs_buffer_postenable()
305 ret = iio_backend_data_format_set(st->back, 0, &fmt); in ad3552r_hs_buffer_postenable()
309 ret = iio_backend_data_stream_enable(st->back); in ad3552r_hs_buffer_postenable()
316 /* Back to simple SPI, not using update to avoid read. */ in ad3552r_hs_buffer_postenable()
317 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
323 * Back bus to simple SPI, this must be executed together with above in ad3552r_hs_buffer_postenable()
326 st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_postenable()
329 iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_postenable()
333 * Back to SDR. In DDR we cannot read, whatever the mode is, so not in ad3552r_hs_buffer_postenable()
336 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
337 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, in ad3552r_hs_buffer_postenable()
338 st->config_d, 1); in ad3552r_hs_buffer_postenable()
341 /* Back to single instruction mode, disabling loop. */ in ad3552r_hs_buffer_postenable()
342 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, in ad3552r_hs_buffer_postenable()
354 ret = iio_backend_data_stream_disable(st->back); in ad3552r_hs_buffer_predisable()
359 * Set us to simple SPI, even if still in ddr, so to be able to write in ad3552r_hs_buffer_predisable()
362 ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_predisable()
367 * Back to SDR (in DDR we cannot read, whatever the mode is, so not in ad3552r_hs_buffer_predisable()
370 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_predisable()
371 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_predisable()
373 st->config_d, 1); in ad3552r_hs_buffer_predisable()
377 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_predisable()
382 * Back to simple SPI for secondary region too now, so to be able to in ad3552r_hs_buffer_predisable()
391 /* Back to single instruction mode, disabling loop. */ in ad3552r_hs_buffer_predisable()
422 st->reset_gpio = devm_gpiod_get_optional(st->dev, in ad3552r_hs_reset()
424 if (IS_ERR(st->reset_gpio)) in ad3552r_hs_reset()
425 return PTR_ERR(st->reset_gpio); in ad3552r_hs_reset()
427 if (st->reset_gpio) { in ad3552r_hs_reset()
429 gpiod_set_value_cansleep(st->reset_gpio, 0); in ad3552r_hs_reset()
447 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
452 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
458 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
462 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
467 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
473 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
485 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), in ad3552r_hs_setup_custom_gain()
490 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), in ad3552r_hs_setup_custom_gain()
499 if (reg > st->model_data->max_reg_addr) in ad3552r_hs_reg_access()
500 return -EINVAL; in ad3552r_hs_reg_access()
504 * or 16 bit data, not 24. So, also to avoid to check any proper read in ad3552r_hs_reg_access()
505 * alignment, supporting only 8-bit readings here. in ad3552r_hs_reg_access()
510 return st->data->bus_reg_write(st->back, reg, writeval, 1); in ad3552r_hs_reg_access()
516 struct ad3552r_hs_state *st = file_inode(f)->i_private; in ad3552r_hs_show_data_source()
520 guard(mutex)(&st->lock); in ad3552r_hs_show_data_source()
522 ret = iio_backend_data_source_get(st->back, 0, &type); in ad3552r_hs_show_data_source()
534 return -EINVAL; in ad3552r_hs_show_data_source()
546 struct ad3552r_hs_state *st = file_inode(f)->i_private; in ad3552r_hs_write_data_source()
550 guard(mutex)(&st->lock); in ad3552r_hs_write_data_source()
552 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, userbuf, in ad3552r_hs_write_data_source()
572 return -EINVAL; in ad3552r_hs_write_data_source()
591 len += scnprintf(buf + len, PAGE_SIZE - len, "%s ", in ad3552r_hs_show_data_source_avail()
594 buf[len - 1] = '\n'; in ad3552r_hs_show_data_source_avail()
622 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_setup()
626 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
638 * Caching config_d, needed to restore it after streaming, in ad3552r_hs_setup()
639 * and also, to detect possible DDR read, that's not allowed. in ad3552r_hs_setup()
641 ret = st->data->bus_reg_read(st->back, in ad3552r_hs_setup()
643 &st->config_d, 1); in ad3552r_hs_setup()
658 if (id != st->model_data->chip_id) in ad3552r_hs_setup()
659 dev_warn(st->dev, in ad3552r_hs_setup()
661 id, st->model_data->chip_id); in ad3552r_hs_setup()
663 dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name); in ad3552r_hs_setup()
666 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, in ad3552r_hs_setup()
671 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
681 ret = ad3552r_get_ref_voltage(st->dev, &val); in ad3552r_hs_setup()
694 ret = ad3552r_get_drive_strength(st->dev, &val); in ad3552r_hs_setup()
696 st->config_d |= in ad3552r_hs_setup()
699 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
701 st->config_d, 1); in ad3552r_hs_setup()
706 device_for_each_child_node_scoped(st->dev, child) { in ad3552r_hs_setup()
709 return dev_err_probe(st->dev, ret, in ad3552r_hs_setup()
712 ret = ad3552r_get_output_range(st->dev, st->model_data, child, in ad3552r_hs_setup()
714 if (ret && ret != -ENOENT) in ad3552r_hs_setup()
716 if (ret == -ENOENT) { in ad3552r_hs_setup()
717 ret = ad3552r_get_custom_gain(st->dev, child, in ad3552r_hs_setup()
718 &st->ch_data[ch].p, in ad3552r_hs_setup()
719 &st->ch_data[ch].n, in ad3552r_hs_setup()
720 &st->ch_data[ch].rfb, in ad3552r_hs_setup()
721 &st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
725 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, in ad3552r_hs_setup()
726 st->ch_data[ch].n, in ad3552r_hs_setup()
727 st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
728 offset = abs(st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
730 st->ch_data[ch].range_override = 1; in ad3552r_hs_setup()
737 st->ch_data[ch].range = range; in ad3552r_hs_setup()
744 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); in ad3552r_hs_setup()
794 dev_warn(st->dev, "can't set debugfs in driver dir\n"); in ad3552r_hs_debugfs_init()
810 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); in ad3552r_hs_probe()
812 return -ENOMEM; in ad3552r_hs_probe()
815 st->dev = &pdev->dev; in ad3552r_hs_probe()
817 st->data = dev_get_platdata(st->dev); in ad3552r_hs_probe()
818 if (!st->data) in ad3552r_hs_probe()
819 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); in ad3552r_hs_probe()
821 st->back = devm_iio_backend_get(&pdev->dev, NULL); in ad3552r_hs_probe()
822 if (IS_ERR(st->back)) in ad3552r_hs_probe()
823 return PTR_ERR(st->back); in ad3552r_hs_probe()
825 ret = devm_iio_backend_enable(&pdev->dev, st->back); in ad3552r_hs_probe()
829 st->model_data = device_get_match_data(&pdev->dev); in ad3552r_hs_probe()
830 if (!st->model_data) in ad3552r_hs_probe()
831 return -ENODEV; in ad3552r_hs_probe()
833 indio_dev->name = "ad3552r"; in ad3552r_hs_probe()
834 indio_dev->modes = INDIO_DIRECT_MODE; in ad3552r_hs_probe()
835 indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops; in ad3552r_hs_probe()
836 indio_dev->channels = ad3552r_hs_channels; in ad3552r_hs_probe()
837 indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels); in ad3552r_hs_probe()
838 indio_dev->info = &ad3552r_hs_info; in ad3552r_hs_probe()
840 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); in ad3552r_hs_probe()
848 ret = devm_iio_device_register(&pdev->dev, indio_dev); in ad3552r_hs_probe()
852 ret = devm_mutex_init(&pdev->dev, &st->lock); in ad3552r_hs_probe()
872 .name = "ad3552r-hs",
881 MODULE_DESCRIPTION("AD3552R Driver - High Speed version");