Lines Matching full:st
72 static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val, in ad3552r_hs_reg_read() argument
76 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
78 return st->data->bus_reg_read(st->back, reg, val, xfer_size); in ad3552r_hs_reg_read()
81 static int ad3552r_hs_set_data_source(struct ad3552r_hs_state *st, in ad3552r_hs_set_data_source() argument
86 for (i = 0; i < st->model_data->num_hw_channels; ++i) { in ad3552r_hs_set_data_source()
87 ret = iio_backend_data_source_set(st->back, i, type); in ad3552r_hs_set_data_source()
95 static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg, in ad3552r_hs_update_reg_bits() argument
101 ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size); in ad3552r_hs_update_reg_bits()
107 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); in ad3552r_hs_update_reg_bits()
114 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_read_raw() local
126 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * in ad3552r_hs_read_raw()
127 st->model_data->num_spi_data_lanes * 2, in ad3552r_hs_read_raw()
134 ret = ad3552r_hs_reg_read(st, in ad3552r_hs_read_raw()
142 *val = st->ch_data[ch].scale_int; in ad3552r_hs_read_raw()
143 *val2 = st->ch_data[ch].scale_dec; in ad3552r_hs_read_raw()
146 *val = st->ch_data[ch].offset_int; in ad3552r_hs_read_raw()
147 *val2 = st->ch_data[ch].offset_dec; in ad3552r_hs_read_raw()
158 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_write_raw() local
166 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_write_raw()
177 static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st) in ad3552r_hs_set_bus_io_mode_hs() argument
181 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_bus_io_mode_hs()
186 return st->data->bus_set_io_mode(st->back, bus_mode); in ad3552r_hs_set_bus_io_mode_hs()
189 static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st) in ad3552r_hs_set_target_io_mode_hs() argument
197 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_target_io_mode_hs()
206 return st->data->bus_reg_write(st->back, in ad3552r_hs_set_target_io_mode_hs()
215 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_buffer_postenable() local
223 st->single_channel = true; in ad3552r_hs_buffer_postenable()
228 st->single_channel = true; in ad3552r_hs_buffer_postenable()
233 st->single_channel = false; in ad3552r_hs_buffer_postenable()
247 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_buffer_postenable()
258 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
265 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
271 st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
272 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
274 st->config_d, 1); in ad3552r_hs_buffer_postenable()
278 ret = iio_backend_ddr_enable(st->back); in ad3552r_hs_buffer_postenable()
288 ret = ad3552r_hs_set_target_io_mode_hs(st); in ad3552r_hs_buffer_postenable()
293 ret = ad3552r_hs_set_bus_io_mode_hs(st); in ad3552r_hs_buffer_postenable()
301 ret = iio_backend_data_transfer_addr(st->back, val); in ad3552r_hs_buffer_postenable()
305 ret = iio_backend_data_format_set(st->back, 0, &fmt); in ad3552r_hs_buffer_postenable()
309 ret = iio_backend_data_stream_enable(st->back); in ad3552r_hs_buffer_postenable()
317 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
326 st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_postenable()
329 iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_postenable()
336 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
337 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, in ad3552r_hs_buffer_postenable()
338 st->config_d, 1); in ad3552r_hs_buffer_postenable()
342 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, in ad3552r_hs_buffer_postenable()
351 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_buffer_predisable() local
354 ret = iio_backend_data_stream_disable(st->back); in ad3552r_hs_buffer_predisable()
362 ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_predisable()
370 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_predisable()
371 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_predisable()
373 st->config_d, 1); in ad3552r_hs_buffer_predisable()
377 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_predisable()
385 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_predisable()
392 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_buffer_predisable()
402 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st, in ad3552r_hs_set_output_range() argument
412 return ad3552r_hs_update_reg_bits(st, in ad3552r_hs_set_output_range()
418 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) in ad3552r_hs_reset() argument
422 st->reset_gpio = devm_gpiod_get_optional(st->dev, in ad3552r_hs_reset()
424 if (IS_ERR(st->reset_gpio)) in ad3552r_hs_reset()
425 return PTR_ERR(st->reset_gpio); in ad3552r_hs_reset()
427 if (st->reset_gpio) { in ad3552r_hs_reset()
429 gpiod_set_value_cansleep(st->reset_gpio, 0); in ad3552r_hs_reset()
431 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_reset()
443 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st) in ad3552r_hs_scratch_pad_test() argument
447 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
452 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
458 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
462 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
467 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
473 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
480 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st, in ad3552r_hs_setup_custom_gain() argument
485 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), in ad3552r_hs_setup_custom_gain()
490 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), in ad3552r_hs_setup_custom_gain()
497 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_reg_access() local
499 if (reg > st->model_data->max_reg_addr) in ad3552r_hs_reg_access()
508 return ad3552r_hs_reg_read(st, reg, readval, 1); in ad3552r_hs_reg_access()
510 return st->data->bus_reg_write(st->back, reg, writeval, 1); in ad3552r_hs_reg_access()
516 struct ad3552r_hs_state *st = file_inode(f)->i_private; in ad3552r_hs_show_data_source() local
520 guard(mutex)(&st->lock); in ad3552r_hs_show_data_source()
522 ret = iio_backend_data_source_get(st->back, 0, &type); in ad3552r_hs_show_data_source()
546 struct ad3552r_hs_state *st = file_inode(f)->i_private; in ad3552r_hs_write_data_source() local
550 guard(mutex)(&st->lock); in ad3552r_hs_write_data_source()
575 ret = ad3552r_hs_set_data_source(st, source); in ad3552r_hs_write_data_source()
610 static int ad3552r_hs_setup(struct ad3552r_hs_state *st) in ad3552r_hs_setup() argument
617 ret = ad3552r_hs_reset(st); in ad3552r_hs_setup()
622 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_setup()
626 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
633 ret = ad3552r_hs_scratch_pad_test(st); in ad3552r_hs_setup()
641 ret = st->data->bus_reg_read(st->back, in ad3552r_hs_setup()
643 &st->config_d, 1); in ad3552r_hs_setup()
647 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1); in ad3552r_hs_setup()
653 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1); in ad3552r_hs_setup()
658 if (id != st->model_data->chip_id) in ad3552r_hs_setup()
659 dev_warn(st->dev, in ad3552r_hs_setup()
661 id, st->model_data->chip_id); in ad3552r_hs_setup()
663 dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name); in ad3552r_hs_setup()
666 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, in ad3552r_hs_setup()
671 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
677 ret = ad3552r_hs_set_data_source(st, IIO_BACKEND_EXTERNAL); in ad3552r_hs_setup()
681 ret = ad3552r_get_ref_voltage(st->dev, &val); in ad3552r_hs_setup()
687 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_setup()
694 ret = ad3552r_get_drive_strength(st->dev, &val); in ad3552r_hs_setup()
696 st->config_d |= in ad3552r_hs_setup()
699 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
701 st->config_d, 1); in ad3552r_hs_setup()
706 device_for_each_child_node_scoped(st->dev, child) { in ad3552r_hs_setup()
709 return dev_err_probe(st->dev, ret, in ad3552r_hs_setup()
712 ret = ad3552r_get_output_range(st->dev, st->model_data, child, in ad3552r_hs_setup()
717 ret = ad3552r_get_custom_gain(st->dev, child, in ad3552r_hs_setup()
718 &st->ch_data[ch].p, in ad3552r_hs_setup()
719 &st->ch_data[ch].n, in ad3552r_hs_setup()
720 &st->ch_data[ch].rfb, in ad3552r_hs_setup()
721 &st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
725 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, in ad3552r_hs_setup()
726 st->ch_data[ch].n, in ad3552r_hs_setup()
727 st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
728 offset = abs(st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
730 st->ch_data[ch].range_override = 1; in ad3552r_hs_setup()
732 ret = ad3552r_hs_setup_custom_gain(st, ch, gain, in ad3552r_hs_setup()
737 st->ch_data[ch].range = range; in ad3552r_hs_setup()
739 ret = ad3552r_hs_set_output_range(st, ch, range); in ad3552r_hs_setup()
744 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); in ad3552r_hs_setup()
786 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_debugfs_init() local
794 dev_warn(st->dev, "can't set debugfs in driver dir\n"); in ad3552r_hs_debugfs_init()
798 debugfs_create_file("data_source", 0600, d, st, in ad3552r_hs_debugfs_init()
800 debugfs_create_file("data_source_available", 0600, d, st, in ad3552r_hs_debugfs_init()
806 struct ad3552r_hs_state *st; in ad3552r_hs_probe() local
810 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); in ad3552r_hs_probe()
814 st = iio_priv(indio_dev); in ad3552r_hs_probe()
815 st->dev = &pdev->dev; in ad3552r_hs_probe()
817 st->data = dev_get_platdata(st->dev); in ad3552r_hs_probe()
818 if (!st->data) in ad3552r_hs_probe()
819 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); in ad3552r_hs_probe()
821 st->back = devm_iio_backend_get(&pdev->dev, NULL); in ad3552r_hs_probe()
822 if (IS_ERR(st->back)) in ad3552r_hs_probe()
823 return PTR_ERR(st->back); in ad3552r_hs_probe()
825 ret = devm_iio_backend_enable(&pdev->dev, st->back); in ad3552r_hs_probe()
829 st->model_data = device_get_match_data(&pdev->dev); in ad3552r_hs_probe()
830 if (!st->model_data) in ad3552r_hs_probe()
840 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); in ad3552r_hs_probe()
844 ret = ad3552r_hs_setup(st); in ad3552r_hs_probe()
852 ret = devm_mutex_init(&pdev->dev, &st->lock); in ad3552r_hs_probe()