1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2013-2014 Analog Devices Inc.
6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
9  *  - XADC hardmacro: Xilinx UG480
10  *  - ZYNQ XADC interface: Xilinx UG585
11  *  - AXI XADC interface: Xilinx PG019
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/trigger.h>
33 #include <linux/iio/trigger_consumer.h>
34 #include <linux/iio/triggered_buffer.h>
36 #include "xilinx-xadc.h"
117  * overloaded by the interrupts that it soft-lockups. For this reason the driver
126 	writel(val, xadc->base + reg);  in xadc_write_reg()
132 	*val = readl(xadc->base + reg);  in xadc_read_reg()
169 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
170 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
173 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
183 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
187 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
197 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
199 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
201 		ret = -EIO;  in xadc_zynq_write_adc_reg()
220 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
224 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
233 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
234 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
236 		ret = -EIO;  in xadc_zynq_read_adc_reg()
272 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
275 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
276 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
279 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
286 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
288 	/* if still pending some alarm re-trigger the timer */  in xadc_zynq_unmask_worker()
289 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
290 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
304 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
309 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
316 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
321 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
332 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
335 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
359 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
361 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
363 		return -EINVAL;  in xadc_zynq_setup()
366 		ret = clk_set_rate(xadc->clk,  in xadc_zynq_setup()
392 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
398 		ret = clk_set_rate(xadc->clk, pcap_rate);  in xadc_zynq_setup()
428 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
439 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
448 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
459 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
474 	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_read_adc_reg()
484 	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_write_adc_reg()
515 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
516 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
520 		 * The order of the bits in the AXI-XADC status register does  in xadc_axi_interrupt_handler()
542 	 * The order of the bits in the AXI-XADC status register does not match  in xadc_axi_update_alarm()
550 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
555 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
560 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
572 	/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
588 	 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
612 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
614 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
621 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
633 	data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,  in xadc_update_scan_mode()
634 				   n, sizeof(*xadc->data), GFP_KERNEL);  in xadc_update_scan_mode()
636 		return -ENOMEM;  in xadc_update_scan_mode()
638 	memset(data, 0, n * sizeof(*xadc->data));  in xadc_update_scan_mode()
639 	xadc->data = data;  in xadc_update_scan_mode()
668 		return XADC_REG_VAUX(scan_index - 16);  in xadc_scan_index_to_channel()
675 	struct iio_dev *indio_dev = pf->indio_dev;  in xadc_trigger_handler()
680 	if (!xadc->data)  in xadc_trigger_handler()
686 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
690 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
693 	iio_trigger_notify_done(indio_dev->trig);  in xadc_trigger_handler()
706 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
710 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
711 			ret = -EBUSY;  in xadc_trigger_set_state()
714 			xadc->trigger = trigger;  in xadc_trigger_set_state()
715 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
725 		xadc->trigger = NULL;  in xadc_trigger_set_state()
728 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
736 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
739 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
751 	struct device *dev = indio_dev->dev.parent;  in xadc_alloc_trigger()
755 	trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,  in xadc_alloc_trigger()
758 		return ERR_PTR(-ENOMEM);  in xadc_alloc_trigger()
760 	trig->ops = &xadc_trigger_ops;  in xadc_alloc_trigger()
775 	 * As per datasheet the power-down bits are don't care in the  in xadc_power_adc_b()
776 	 * UltraScale, but as per reality setting the power-down bit for the  in xadc_power_adc_b()
777 	 * non-existing ADC-B powers down the main ADC, so just return and don't  in xadc_power_adc_b()
780 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_power_adc_b()
783 	/* Powerdown the ADC-B when it is not needed. */  in xadc_power_adc_b()
803 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_get_seq_mode()
806 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
824 	for (i = 0; i < indio_dev->num_channels; i++)  in xadc_postdisable()
825 		scan_mask |= BIT(indio_dev->channels[i].scan_index);  in xadc_postdisable()
856 	scan_mask = *indio_dev->active_scan_mask;  in xadc_preenable()
864 	 * In simultaneous mode the upper and lower aux channels are samples at  in xadc_preenable()
918 	unsigned int bits = chan->scan_type.realbits;  in xadc_read_raw()
925 			return -EBUSY;  in xadc_read_raw()
926 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
930 		val16 >>= chan->scan_type.shift;  in xadc_read_raw()
931 		if (chan->scan_type.sign == 'u')  in xadc_read_raw()
934 			*val = sign_extend32(val16, bits - 1);  in xadc_read_raw()
938 		switch (chan->type) {  in xadc_read_raw()
941 			switch (chan->address) {  in xadc_read_raw()
959 			*val = xadc->ops->temp_scale;  in xadc_read_raw()
963 			return -EINVAL;  in xadc_read_raw()
967 		*val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);  in xadc_read_raw()
977 		return -EINVAL;  in xadc_read_raw()
987 		return -EINVAL;  in xadc_write_samplerate()
990 		return -EINVAL;  in xadc_write_samplerate()
1024 		return -EINVAL;  in xadc_write_raw()
1072 		.shift = 16 - (_bits), \
1092 		.shift = 16 - (_bits), \
1180 		.compatible = "xlnx,zynq-xadc-1.00.a",
1183 		.compatible = "xlnx,axi-xadc-1.00.a",
1186 		.compatible = "xlnx,system-management-wiz-1.3",
1195 	struct device *dev = indio_dev->dev.parent;  in xadc_parse_dt()
1210 	ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);  in xadc_parse_dt()
1212 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1214 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1216 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1218 		return -EINVAL;  in xadc_parse_dt()
1220 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1221 		ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);  in xadc_parse_dt()
1225 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1229 				ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);  in xadc_parse_dt()
1231 				return -EINVAL;  in xadc_parse_dt()
1234 				ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);  in xadc_parse_dt()
1236 				return -EINVAL;  in xadc_parse_dt()
1241 	if (xadc->ops->type == XADC_TYPE_S7) {  in xadc_parse_dt()
1251 		return -ENOMEM;  in xadc_parse_dt()
1268 			chan->scan_type.sign = 's';  in xadc_parse_dt()
1271 			chan->scan_index = 11;  in xadc_parse_dt()
1272 			chan->address = XADC_REG_VPVN;  in xadc_parse_dt()
1274 			chan->scan_index = 15 + reg;  in xadc_parse_dt()
1275 			chan->address = XADC_REG_VAUX(reg - 1);  in xadc_parse_dt()
1290 	indio_dev->num_channels = num_channels;  in xadc_parse_dt()
1291 	indio_dev->channels = devm_krealloc_array(dev, channels,  in xadc_parse_dt()
1295 	if (!indio_dev->channels)  in xadc_parse_dt()
1296 		indio_dev->channels = channels;  in xadc_parse_dt()
1303 	[XADC_TYPE_US] = "xilinx-system-monitor",
1315 	struct device *dev = &pdev->dev;  in xadc_probe()
1327 		return -EINVAL;  in xadc_probe()
1331 	    (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))  in xadc_probe()
1336 		return -ENOMEM;  in xadc_probe()
1339 	xadc->ops = ops;  in xadc_probe()
1340 	init_completion(&xadc->completion);  in xadc_probe()
1341 	mutex_init(&xadc->mutex);  in xadc_probe()
1342 	spin_lock_init(&xadc->lock);  in xadc_probe()
1343 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1345 	xadc->base = devm_platform_ioremap_resource(pdev, 0);  in xadc_probe()
1346 	if (IS_ERR(xadc->base))  in xadc_probe()
1347 		return PTR_ERR(xadc->base);  in xadc_probe()
1349 	indio_dev->name = xadc_type_names[xadc->ops->type];  in xadc_probe()
1350 	indio_dev->modes = INDIO_DIRECT_MODE;  in xadc_probe()
1351 	indio_dev->info = &xadc_info;  in xadc_probe()
1357 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1366 			xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1367 			if (IS_ERR(xadc->convst_trigger))  in xadc_probe()
1368 				return PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1370 			xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1372 			if (IS_ERR(xadc->samplerate_trigger))  in xadc_probe()
1373 				return PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1377 	xadc->clk = devm_clk_get_enabled(dev, NULL);  in xadc_probe()
1378 	if (IS_ERR(xadc->clk))  in xadc_probe()
1379 		return PTR_ERR(xadc->clk);  in xadc_probe()
1383 	 * resulting interrupt storm will soft-lock the system.  in xadc_probe()
1385 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1398 		ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,  in xadc_probe()
1404 					       &xadc->zynq_unmask_work);  in xadc_probe()
1409 	ret = xadc->ops->setup(pdev, indio_dev, irq);  in xadc_probe()
1415 			&xadc->threshold[i]);  in xadc_probe()
1422 	for (i = 0; i < indio_dev->num_channels; i++) {  in xadc_probe()
1423 		if (indio_dev->channels[i].scan_type.sign == 's')  in xadc_probe()
1424 			bipolar_mask |= BIT(indio_dev->channels[i].scan_index);  in xadc_probe()
1436 	/* Go to non-buffered mode */  in xadc_probe()
1452 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1453 MODULE_DESCRIPTION("Xilinx XADC IIO driver");