Lines Matching +full:adc +full:- +full:use +full:- +full:res
1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
16 #include <linux/iio/timer/stm32-lptim-trigger.h>
17 #include <linux/iio/timer/stm32-timer-trigger.h>
26 #include <linux/nvmem-consumer.h>
31 #include "stm32-adc-core.h"
36 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
58 /* extsel - trigger mux selection value */
84 STM32_ADC_INT_CH_NONE = -1,
94 * struct stm32_adc_ic - ADC internal channels
112 * struct stm32_adc_trig_info - ADC trigger info
122 * struct stm32_adc_calib - optional adc calibration data
132 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
144 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
154 * struct stm32_adc_regspec - stm32 registers definition
163 * @res: resolution selection register & bitfield
182 const struct stm32_adc_regs res; member
196 * struct stm32_adc_cfg - stm32 compatible configuration data
205 * @prepare: optional prepare routine (power-up, enable)
208 * @unprepare: optional unprepare routine (disable, power-down)
210 * @smp_cycles: programmable sampling time (ADC clock cycles)
232 * struct stm32_adc - private data of each ADC IIO instance
233 * @common: reference to ADC block common data
234 * @offset: ADC instance register offset in ADC block
238 * @clk: clock for this adc instance
239 * @irq: interrupt for this adc instance
243 * @res: data resolution (e.g. RES bitfield value)
249 * @difsel: bitmask to set single-ended/differential channel
270 u32 res; member
293 * struct stm32_adc_info - stm32 ADC, per instance config data
305 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
317 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
336 * stm32f4_sq - describe regular sequence registers
337 * - L: sequence len (register & bit field)
338 * - SQ1..SQ16: sequence entries (register & bit field)
383 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
410 /* STM32F4 programmable sampling time (ADC clock cycles) */
425 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
476 * stm32h7_smp_bits - describe sampling time register index & bit fields
504 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
519 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
525 /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */
540 .res = { STM32H7_ADC_CFGR, STM32MP13_RES_MASK, STM32MP13_RES_SHIFT },
561 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
571 * STM32 ADC registers access routines
572 * @adc: stm32 adc instance
573 * @reg: reg offset in adc instance
578 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) in stm32_adc_readl() argument
580 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
583 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
589 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) in stm32_adc_readw() argument
591 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
594 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) in stm32_adc_writel() argument
596 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
599 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits() argument
603 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
604 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); in stm32_adc_set_bits()
605 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
608 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits_common() argument
610 spin_lock(&adc->common->lock); in stm32_adc_set_bits_common()
611 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, in stm32_adc_set_bits_common()
612 adc->common->base + reg); in stm32_adc_set_bits_common()
613 spin_unlock(&adc->common->lock); in stm32_adc_set_bits_common()
616 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits() argument
620 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
621 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); in stm32_adc_clr_bits()
622 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
625 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits_common() argument
627 spin_lock(&adc->common->lock); in stm32_adc_clr_bits_common()
628 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, in stm32_adc_clr_bits_common()
629 adc->common->base + reg); in stm32_adc_clr_bits_common()
630 spin_unlock(&adc->common->lock); in stm32_adc_clr_bits_common()
634 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
635 * @adc: stm32 adc instance
637 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) in stm32_adc_conv_irq_enable() argument
639 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
640 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
644 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
645 * @adc: stm32 adc instance
647 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) in stm32_adc_conv_irq_disable() argument
649 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
650 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
653 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) in stm32_adc_ovr_irq_enable() argument
655 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
656 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
659 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) in stm32_adc_ovr_irq_disable() argument
661 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
662 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
665 static void stm32_adc_set_res(struct stm32_adc *adc) in stm32_adc_set_res() argument
667 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res() local
670 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
671 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
672 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
678 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_stop() local
680 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
681 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
683 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
691 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_start() local
694 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
698 stm32_adc_set_res(adc); in stm32_adc_hw_start()
700 if (adc->cfg->prepare) { in stm32_adc_hw_start()
701 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
709 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
716 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_int_ch_enable() local
720 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_enable()
725 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); in stm32_adc_int_ch_enable()
726 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_enable()
727 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_enable()
730 dev_dbg(&indio_dev->dev, "Enable VDDCPU\n"); in stm32_adc_int_ch_enable()
731 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_enable()
732 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_enable()
735 dev_dbg(&indio_dev->dev, "Enable VDDQ_DDR\n"); in stm32_adc_int_ch_enable()
736 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_enable()
737 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_enable()
740 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); in stm32_adc_int_ch_enable()
741 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_enable()
742 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_enable()
745 dev_dbg(&indio_dev->dev, "Enable VBAT\n"); in stm32_adc_int_ch_enable()
746 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_enable()
747 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_enable()
753 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) in stm32_adc_int_ch_disable() argument
758 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_disable()
763 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_disable()
764 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_disable()
767 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_disable()
768 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_disable()
771 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_disable()
772 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_disable()
775 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_disable()
776 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_disable()
779 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_disable()
780 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_disable()
787 * stm32f4_adc_start_conv() - Start conversions for regular channels.
789 * @dma: use dma to transfer conversion result
793 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
798 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_start_conv() local
800 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_start_conv()
803 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_start_conv()
806 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); in stm32f4_adc_start_conv()
808 /* Wait for Power-up time (tSTAB from datasheet) */ in stm32f4_adc_start_conv()
812 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) in stm32f4_adc_start_conv()
813 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); in stm32f4_adc_start_conv()
818 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_stop_conv() local
820 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); in stm32f4_adc_stop_conv()
821 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); in stm32f4_adc_stop_conv()
823 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_stop_conv()
824 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_stop_conv()
830 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_irq_clear() local
832 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
837 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_start_conv() local
847 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
848 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); in stm32h7_adc_start_conv()
850 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); in stm32h7_adc_start_conv()
851 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
853 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32h7_adc_start_conv()
858 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_stop_conv() local
862 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); in stm32h7_adc_stop_conv()
868 dev_warn(&indio_dev->dev, "stop failed\n"); in stm32h7_adc_stop_conv()
871 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); in stm32h7_adc_stop_conv()
876 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_irq_clear() local
878 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
883 struct stm32_adc *adc = iio_priv(indio_dev); in stm32mp13_adc_start_conv() local
886 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, in stm32mp13_adc_start_conv()
889 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32mp13_adc_start_conv()
894 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_exit_pwr_down() local
898 /* Exit deep power down, then enable ADC voltage regulator */ in stm32h7_adc_exit_pwr_down()
899 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
900 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); in stm32h7_adc_exit_pwr_down()
902 if (adc->cfg->has_boostmode && in stm32h7_adc_exit_pwr_down()
903 adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
904 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_exit_pwr_down()
907 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
916 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
917 dev_err(&indio_dev->dev, "Failed to exit power down\n"); in stm32h7_adc_exit_pwr_down()
923 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) in stm32h7_adc_enter_pwr_down() argument
925 if (adc->cfg->has_boostmode) in stm32h7_adc_enter_pwr_down()
926 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_enter_pwr_down()
928 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ in stm32h7_adc_enter_pwr_down()
929 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_enter_pwr_down()
934 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_enable() local
938 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); in stm32h7_adc_enable()
940 /* Poll for ADRDY to be set (after adc startup time) */ in stm32h7_adc_enable()
945 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_enable()
946 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
949 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); in stm32h7_adc_enable()
957 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_disable() local
961 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) in stm32h7_adc_disable()
964 /* Disable ADC and wait until it's effectively disabled */ in stm32h7_adc_disable()
965 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_disable()
970 dev_warn(&indio_dev->dev, "Failed to disable\n"); in stm32h7_adc_disable()
974 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
976 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
980 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_read_selfcalib() local
986 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_read_selfcalib()
988 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_read_selfcalib()
995 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_read_selfcalib()
999 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_read_selfcalib()
1000 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
1001 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
1005 adc->cal.lincal_saved = true; in stm32h7_adc_read_selfcalib()
1011 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
1013 * Note: ADC must be enabled, with no on-going conversions.
1017 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_restore_selfcalib() local
1022 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_restore_selfcalib()
1028 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
1029 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); in stm32h7_adc_restore_selfcalib()
1030 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1035 dev_err(&indio_dev->dev, "Failed to write calfact\n"); in stm32h7_adc_restore_selfcalib()
1041 * - It ensures bits LINCALRDYW[6..1] are kept cleared in stm32h7_adc_restore_selfcalib()
1043 * - BTW, bit clear triggers a read, then check data has been in stm32h7_adc_restore_selfcalib()
1046 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1051 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_restore_selfcalib()
1054 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_restore_selfcalib()
1055 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
1056 dev_err(&indio_dev->dev, "calfact not consistent\n"); in stm32h7_adc_restore_selfcalib()
1057 return -EIO; in stm32h7_adc_restore_selfcalib()
1067 * Fixed timeout value for ADC calibration.
1069 * - low clock frequency
1070 * - maximum prescalers
1072 * - 131,072 ADC clock cycle for the linear calibration
1073 * - 20 ADC clock cycle for the offset calibration
1080 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
1083 * Note: Must be called once ADC is out of power down.
1090 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_selfcalib() local
1095 if (adc->cfg->has_linearcal && do_lincal) in stm32h7_adc_selfcalib()
1097 /* ADC must be disabled for calibration */ in stm32h7_adc_selfcalib()
1102 * - Offset calibration for single ended inputs in stm32h7_adc_selfcalib()
1103 * - No linearity calibration (do it later, before reading it) in stm32h7_adc_selfcalib()
1105 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1108 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1113 dev_err(&indio_dev->dev, "calibration (single-ended) error %d\n", ret); in stm32h7_adc_selfcalib()
1119 * - Offset calibration for differential input in stm32h7_adc_selfcalib()
1120 * - Linearity calibration (needs to be done only once for single/diff) in stm32h7_adc_selfcalib()
1123 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1124 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1129 dev_err(&indio_dev->dev, "calibration (diff%s) error %d\n", in stm32h7_adc_selfcalib()
1135 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1141 * stm32h7_adc_check_selfcalib() - Check linear calibration status
1150 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_check_selfcalib() local
1153 if (adc->cal.lincal_saved) in stm32h7_adc_check_selfcalib()
1157 * Check if linear calibration factors are available in ADC registers, in stm32h7_adc_check_selfcalib()
1160 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK; in stm32h7_adc_check_selfcalib()
1168 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
1171 * Configure channels as single ended or differential before enabling ADC.
1172 * Enable ADC.
1174 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
1175 * - Only one input is selected for single ended (e.g. 'vinp')
1176 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
1180 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_prepare() local
1188 if (adc->cfg->has_linearcal) in stm32h7_adc_prepare()
1198 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); in stm32h7_adc_prepare()
1204 if (adc->cfg->has_linearcal) { in stm32h7_adc_prepare()
1205 if (!adc->cal.lincal_saved) in stm32h7_adc_prepare()
1214 if (adc->cfg->has_presel) in stm32h7_adc_prepare()
1215 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
1222 stm32_adc_int_ch_disable(adc); in stm32h7_adc_prepare()
1224 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_prepare()
1231 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_unprepare() local
1233 if (adc->cfg->has_presel) in stm32h7_adc_unprepare()
1234 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); in stm32h7_adc_unprepare()
1236 stm32_adc_int_ch_disable(adc); in stm32h7_adc_unprepare()
1237 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_unprepare()
1241 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
1247 * Configure ADC scan sequence based on selected channels in scan_mask.
1254 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_conf_scan_seq() local
1255 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1261 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1262 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1265 chan = indio_dev->channels + bit; in stm32_adc_conf_scan_seq()
1272 return -EINVAL; in stm32_adc_conf_scan_seq()
1274 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", in stm32_adc_conf_scan_seq()
1275 __func__, chan->channel, i); in stm32_adc_conf_scan_seq()
1277 val = stm32_adc_readl(adc, sqr[i].reg); in stm32_adc_conf_scan_seq()
1279 val |= chan->channel << sqr[i].shift; in stm32_adc_conf_scan_seq()
1280 stm32_adc_writel(adc, sqr[i].reg, val); in stm32_adc_conf_scan_seq()
1284 return -EINVAL; in stm32_adc_conf_scan_seq()
1287 val = stm32_adc_readl(adc, sqr[0].reg); in stm32_adc_conf_scan_seq()
1289 val |= ((i - 1) << sqr[0].shift); in stm32_adc_conf_scan_seq()
1290 stm32_adc_writel(adc, sqr[0].reg, val); in stm32_adc_conf_scan_seq()
1296 * stm32_adc_get_trig_extsel() - Get external trigger selection
1300 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1305 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_extsel() local
1309 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1316 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1317 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1321 return -EINVAL; in stm32_adc_get_trig_extsel()
1325 * stm32_adc_set_trig() - Set a regular trigger
1330 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1331 * - if HW trigger enabled, set source & polarity
1336 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig() local
1348 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1351 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1352 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1353 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1354 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1355 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1356 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1357 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1366 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig_pol() local
1368 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1376 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_pol() local
1378 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1382 "rising-edge", "falling-edge", "both-edges",
1393 * stm32_adc_single_conv() - Performs a single conversion
1396 * @res: conversion result
1399 * - Apply sampling time settings
1400 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1401 * - Use SW trigger
1402 * - Start conversion, then wait for interrupt completion.
1406 int *res) in stm32_adc_single_conv() argument
1408 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_single_conv() local
1409 struct device *dev = indio_dev->dev.parent; in stm32_adc_single_conv()
1410 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1415 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1417 adc->bufi = 0; in stm32_adc_single_conv()
1424 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1425 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1428 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1429 val &= ~regs->sqr[1].mask; in stm32_adc_single_conv()
1430 val |= chan->channel << regs->sqr[1].shift; in stm32_adc_single_conv()
1431 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1434 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1437 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1439 stm32_adc_conv_irq_enable(adc); in stm32_adc_single_conv()
1441 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1444 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1446 ret = -ETIMEDOUT; in stm32_adc_single_conv()
1450 *res = adc->buffer[0]; in stm32_adc_single_conv()
1454 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1456 stm32_adc_conv_irq_disable(adc); in stm32_adc_single_conv()
1468 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_raw() local
1477 if (chan->type == IIO_VOLTAGE) in stm32_adc_read_raw()
1480 ret = -EINVAL; in stm32_adc_read_raw()
1483 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; in stm32_adc_read_raw()
1489 if (chan->differential) { in stm32_adc_read_raw()
1490 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1491 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1493 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1494 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1499 if (chan->differential) in stm32_adc_read_raw()
1501 *val = -((1 << chan->scan_type.realbits) / 2); in stm32_adc_read_raw()
1507 return -EINVAL; in stm32_adc_read_raw()
1513 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_irq_clear() local
1515 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1521 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_threaded_isr() local
1522 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1523 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1526 if (status & regs->isr_ovr.mask) { in stm32_adc_threaded_isr()
1529 * This requires to stop ADC first. OVR bit state in ISR, in stm32_adc_threaded_isr()
1532 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1533 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); in stm32_adc_threaded_isr()
1534 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); in stm32_adc_threaded_isr()
1544 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_isr() local
1545 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1546 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1548 if (status & regs->isr_ovr.mask) { in stm32_adc_isr()
1554 * re-enabling it (e.g. write 0, then 1 to buffer/enable). in stm32_adc_isr()
1556 stm32_adc_ovr_irq_disable(adc); in stm32_adc_isr()
1557 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1561 if (status & regs->isr_eoc.mask) { in stm32_adc_isr()
1563 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1565 adc->bufi++; in stm32_adc_isr()
1566 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1567 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1568 iio_trigger_poll(indio_dev->trig); in stm32_adc_isr()
1571 complete(&adc->completion); in stm32_adc_isr()
1580 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1584 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1585 * driver, -EINVAL otherwise.
1590 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; in stm32_adc_validate_trigger()
1595 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_watermark() local
1602 * - always one buffer (period) dma is working on in stm32_adc_set_watermark()
1603 * - one buffer (period) driver can push data. in stm32_adc_set_watermark()
1606 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1614 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_update_scan_mode() local
1615 struct device *dev = indio_dev->dev.parent; in stm32_adc_update_scan_mode()
1622 adc->num_conv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev)); in stm32_adc_update_scan_mode()
1636 for (i = 0; i < indio_dev->num_channels; i++) in stm32_adc_fwnode_xlate()
1637 if (indio_dev->channels[i].channel == iiospec->args[0]) in stm32_adc_fwnode_xlate()
1640 return -EINVAL; in stm32_adc_fwnode_xlate()
1644 * stm32_adc_debugfs_reg_access - read or write register value
1650 * To read a value from an ADC register:
1651 * echo [ADC reg offset] > direct_reg_access
1654 * To write a value in a ADC register:
1661 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_reg_access() local
1662 struct device *dev = indio_dev->dev.parent; in stm32_adc_debugfs_reg_access()
1670 stm32_adc_writel(adc, reg, writeval); in stm32_adc_debugfs_reg_access()
1672 *readval = stm32_adc_readl(adc, reg); in stm32_adc_debugfs_reg_access()
1689 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) in stm32_adc_dma_residue() argument
1694 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1695 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1699 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1703 if (i >= adc->bufi) in stm32_adc_dma_residue()
1704 size = i - adc->bufi; in stm32_adc_dma_residue()
1706 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1717 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_buffer_done() local
1718 int residue = stm32_adc_dma_residue(adc); in stm32_adc_dma_buffer_done()
1729 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1731 while (residue >= indio_dev->scan_bytes) { in stm32_adc_dma_buffer_done()
1732 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1736 residue -= indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1737 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1738 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1739 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1745 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_start() local
1750 if (!adc->dma_chan) in stm32_adc_dma_start()
1753 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, in stm32_adc_dma_start()
1754 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1757 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1758 adc->rx_dma_buf, in stm32_adc_dma_start()
1759 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1763 return -EBUSY; in stm32_adc_dma_start()
1765 desc->callback = stm32_adc_dma_buffer_done; in stm32_adc_dma_start()
1766 desc->callback_param = indio_dev; in stm32_adc_dma_start()
1771 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1776 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1783 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_postenable() local
1784 struct device *dev = indio_dev->dev.parent; in stm32_adc_buffer_postenable()
1791 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); in stm32_adc_buffer_postenable()
1793 dev_err(&indio_dev->dev, "Can't set trigger\n"); in stm32_adc_buffer_postenable()
1799 dev_err(&indio_dev->dev, "Can't start dma\n"); in stm32_adc_buffer_postenable()
1803 /* Reset adc buffer index */ in stm32_adc_buffer_postenable()
1804 adc->bufi = 0; in stm32_adc_buffer_postenable()
1806 stm32_adc_ovr_irq_enable(adc); in stm32_adc_buffer_postenable()
1808 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1809 stm32_adc_conv_irq_enable(adc); in stm32_adc_buffer_postenable()
1811 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1826 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_predisable() local
1827 struct device *dev = indio_dev->dev.parent; in stm32_adc_buffer_predisable()
1829 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1830 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1831 stm32_adc_conv_irq_disable(adc); in stm32_adc_buffer_predisable()
1833 stm32_adc_ovr_irq_disable(adc); in stm32_adc_buffer_predisable()
1835 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1836 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1839 dev_err(&indio_dev->dev, "Can't clear trigger\n"); in stm32_adc_buffer_predisable()
1855 struct iio_dev *indio_dev = pf->indio_dev; in stm32_adc_trigger_handler()
1856 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_trigger_handler() local
1858 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1861 adc->bufi = 0; in stm32_adc_trigger_handler()
1862 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1863 pf->timestamp); in stm32_adc_trigger_handler()
1864 iio_trigger_notify_done(indio_dev->trig); in stm32_adc_trigger_handler()
1866 /* re-enable eoc irq */ in stm32_adc_trigger_handler()
1867 stm32_adc_conv_irq_enable(adc); in stm32_adc_trigger_handler()
1885 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_init() local
1887 struct stm32_adc_calib *cal = &adc->cal; in stm32_adc_debugfs_init()
1891 if (!adc->cfg->has_linearcal) in stm32_adc_debugfs_init()
1896 debugfs_create_u32(buf, 0444, d, &cal->lincalfact[i]); in stm32_adc_debugfs_init()
1902 struct device *dev = &indio_dev->dev; in stm32_adc_fw_get_resolution()
1903 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_fw_get_resolution() local
1905 u32 res; in stm32_adc_fw_get_resolution() local
1907 if (device_property_read_u32(dev, "assigned-resolution-bits", &res)) in stm32_adc_fw_get_resolution()
1908 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_fw_get_resolution()
1910 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_fw_get_resolution()
1911 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_fw_get_resolution()
1913 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_fw_get_resolution()
1914 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); in stm32_adc_fw_get_resolution()
1915 return -EINVAL; in stm32_adc_fw_get_resolution()
1918 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); in stm32_adc_fw_get_resolution()
1919 adc->res = i; in stm32_adc_fw_get_resolution()
1924 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) in stm32_adc_smpr_init() argument
1926 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1927 u32 period_ns, shift = smpr->shift, mask = smpr->mask; in stm32_adc_smpr_init()
1928 unsigned int i, smp, r = smpr->reg; in stm32_adc_smpr_init()
1935 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE) in stm32_adc_smpr_init()
1936 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]); in stm32_adc_smpr_init()
1938 /* Determine sampling time (ADC clock cycles) */ in stm32_adc_smpr_init()
1939 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1941 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1946 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ in stm32_adc_smpr_init()
1947 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1954 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_init_one() local
1955 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1957 chan->type = IIO_VOLTAGE; in stm32_adc_chan_init_one()
1958 chan->channel = vinp; in stm32_adc_chan_init_one()
1960 chan->differential = 1; in stm32_adc_chan_init_one()
1961 chan->channel2 = vinn; in stm32_adc_chan_init_one()
1962 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); in stm32_adc_chan_init_one()
1966 chan->datasheet_name = name; in stm32_adc_chan_init_one()
1967 chan->scan_index = scan_index; in stm32_adc_chan_init_one()
1968 chan->indexed = 1; in stm32_adc_chan_init_one()
1969 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) in stm32_adc_chan_init_one()
1970 chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); in stm32_adc_chan_init_one()
1972 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); in stm32_adc_chan_init_one()
1973 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | in stm32_adc_chan_init_one()
1975 chan->scan_type.sign = 'u'; in stm32_adc_chan_init_one()
1976 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1977 chan->scan_type.storagebits = 16; in stm32_adc_chan_init_one()
1978 chan->ext_info = stm32_adc_ext_info; in stm32_adc_chan_init_one()
1980 /* pre-build selected channels mask */ in stm32_adc_chan_init_one()
1981 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1983 /* pre-build diff channels mask */ in stm32_adc_chan_init_one()
1984 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; in stm32_adc_chan_init_one()
1985 /* Also add negative input to pre-selected channels */ in stm32_adc_chan_init_one()
1986 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1990 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) in stm32_adc_get_legacy_chan_count() argument
1992 struct device *dev = &indio_dev->dev; in stm32_adc_get_legacy_chan_count()
1993 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_get_legacy_chan_count()
1996 dev_dbg(&indio_dev->dev, "using legacy channel config\n"); in stm32_adc_get_legacy_chan_count()
1998 ret = device_property_count_u32(dev, "st,adc-channels"); in stm32_adc_get_legacy_chan_count()
1999 if (ret > adc_info->max_channels) { in stm32_adc_get_legacy_chan_count()
2000 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_get_legacy_chan_count()
2001 return -EINVAL; in stm32_adc_get_legacy_chan_count()
2007 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret in stm32_adc_get_legacy_chan_count()
2010 ret = device_property_count_u32(dev, "st,adc-diff-channels"); in stm32_adc_get_legacy_chan_count()
2013 if (ret > adc_info->max_channels) { in stm32_adc_get_legacy_chan_count()
2014 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_get_legacy_chan_count()
2015 return -EINVAL; in stm32_adc_get_legacy_chan_count()
2017 adc->num_diff = ret; in stm32_adc_get_legacy_chan_count()
2023 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); in stm32_adc_get_legacy_chan_count()
2024 if (adc->nsmps > 1 && adc->nsmps != num_channels) { in stm32_adc_get_legacy_chan_count()
2025 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); in stm32_adc_get_legacy_chan_count()
2026 return -EINVAL; in stm32_adc_get_legacy_chan_count()
2033 struct stm32_adc *adc, in stm32_adc_legacy_chan_init() argument
2037 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_legacy_chan_init()
2039 struct device *dev = &indio_dev->dev; in stm32_adc_legacy_chan_init()
2040 u32 num_diff = adc->num_diff; in stm32_adc_legacy_chan_init()
2041 int num_se = nchans - num_diff; in stm32_adc_legacy_chan_init()
2047 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", in stm32_adc_legacy_chan_init()
2050 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); in stm32_adc_legacy_chan_init()
2055 if (diff[i].vinp >= adc_info->max_channels || in stm32_adc_legacy_chan_init()
2056 diff[i].vinn >= adc_info->max_channels) { in stm32_adc_legacy_chan_init()
2057 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", in stm32_adc_legacy_chan_init()
2059 return -EINVAL; in stm32_adc_legacy_chan_init()
2069 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); in stm32_adc_legacy_chan_init()
2071 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret); in stm32_adc_legacy_chan_init()
2076 if (chans[c] >= adc_info->max_channels) { in stm32_adc_legacy_chan_init()
2077 dev_err(&indio_dev->dev, "Invalid channel %d\n", in stm32_adc_legacy_chan_init()
2079 return -EINVAL; in stm32_adc_legacy_chan_init()
2082 /* Channel can't be configured both as single-ended & diff */ in stm32_adc_legacy_chan_init()
2085 dev_err(&indio_dev->dev, "channel %d misconfigured\n", in stm32_adc_legacy_chan_init()
2087 return -EINVAL; in stm32_adc_legacy_chan_init()
2096 if (adc->nsmps > 0) { in stm32_adc_legacy_chan_init()
2097 ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs", in stm32_adc_legacy_chan_init()
2098 smps, adc->nsmps); in stm32_adc_legacy_chan_init()
2111 if (i < adc->nsmps) in stm32_adc_legacy_chan_init()
2115 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_legacy_chan_init()
2124 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_populate_int_ch() local
2133 if (!adc->cfg->regs->or_vddcore.reg) in stm32_adc_populate_int_ch()
2134 dev_warn(&indio_dev->dev, in stm32_adc_populate_int_ch()
2138 if (!adc->cfg->regs->or_vddcpu.reg) in stm32_adc_populate_int_ch()
2139 dev_warn(&indio_dev->dev, in stm32_adc_populate_int_ch()
2143 if (!adc->cfg->regs->or_vddq_ddr.reg) in stm32_adc_populate_int_ch()
2144 dev_warn(&indio_dev->dev, in stm32_adc_populate_int_ch()
2148 if (!adc->cfg->regs->ccr_vref.reg) in stm32_adc_populate_int_ch()
2149 dev_warn(&indio_dev->dev, in stm32_adc_populate_int_ch()
2153 if (!adc->cfg->regs->ccr_vbat.reg) in stm32_adc_populate_int_ch()
2154 dev_warn(&indio_dev->dev, in stm32_adc_populate_int_ch()
2160 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2165 ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); in stm32_adc_populate_int_ch()
2166 if (ret && ret != -ENOENT) { in stm32_adc_populate_int_ch()
2167 return dev_err_probe(indio_dev->dev.parent, ret, in stm32_adc_populate_int_ch()
2170 if (ret == -ENOENT) { in stm32_adc_populate_int_ch()
2171 dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n"); in stm32_adc_populate_int_ch()
2174 dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n"); in stm32_adc_populate_int_ch()
2175 return -ENOENT; in stm32_adc_populate_int_ch()
2177 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2178 adc->vrefint.vrefint_cal = vrefint; in stm32_adc_populate_int_ch()
2186 struct stm32_adc *adc, in stm32_adc_generic_chan_init() argument
2189 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_generic_chan_init()
2190 struct device *dev = &indio_dev->dev; in stm32_adc_generic_chan_init()
2206 return dev_err_probe(dev, -EINVAL, in stm32_adc_generic_chan_init()
2210 strscpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); in stm32_adc_generic_chan_init()
2212 if (ret == -ENOENT) in stm32_adc_generic_chan_init()
2216 } else if (ret != -EINVAL) { in stm32_adc_generic_chan_init()
2220 if (val >= adc_info->max_channels) in stm32_adc_generic_chan_init()
2221 return dev_err_probe(dev, -EINVAL, in stm32_adc_generic_chan_init()
2225 ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2); in stm32_adc_generic_chan_init()
2226 /* diff-channels is optional */ in stm32_adc_generic_chan_init()
2229 if (vin[0] != val || vin[1] >= adc_info->max_channels) in stm32_adc_generic_chan_init()
2230 return dev_err_probe(dev, -EINVAL, in stm32_adc_generic_chan_init()
2231 "Invalid channel in%d-in%d\n", in stm32_adc_generic_chan_init()
2233 } else if (ret != -EINVAL) { in stm32_adc_generic_chan_init()
2235 "Invalid diff-channels property\n"); in stm32_adc_generic_chan_init()
2242 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val); in stm32_adc_generic_chan_init()
2243 /* st,min-sample-time-ns is optional */ in stm32_adc_generic_chan_init()
2244 if (ret && ret != -EINVAL) in stm32_adc_generic_chan_init()
2246 "Invalid st,min-sample-time-ns property\n"); in stm32_adc_generic_chan_init()
2248 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); in stm32_adc_generic_chan_init()
2250 stm32_adc_smpr_init(adc, vin[1], val); in stm32_adc_generic_chan_init()
2260 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_fw_init() local
2261 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_fw_init()
2267 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; in stm32_adc_chan_fw_init()
2269 num_channels = device_get_child_node_count(&indio_dev->dev); in stm32_adc_chan_fw_init()
2274 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); in stm32_adc_chan_fw_init()
2276 dev_err(indio_dev->dev.parent, "No channel found\n"); in stm32_adc_chan_fw_init()
2277 return -ENODATA; in stm32_adc_chan_fw_init()
2285 if (num_channels > adc_info->max_channels) { in stm32_adc_chan_fw_init()
2286 dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", in stm32_adc_chan_fw_init()
2287 num_channels, adc_info->max_channels); in stm32_adc_chan_fw_init()
2288 return -EINVAL; in stm32_adc_chan_fw_init()
2294 channels = devm_kcalloc(&indio_dev->dev, num_channels, in stm32_adc_chan_fw_init()
2297 return -ENOMEM; in stm32_adc_chan_fw_init()
2300 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, in stm32_adc_chan_fw_init()
2301 timestamping ? num_channels - 1 : num_channels); in stm32_adc_chan_fw_init()
2303 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); in stm32_adc_chan_fw_init()
2311 timestamp->type = IIO_TIMESTAMP; in stm32_adc_chan_fw_init()
2312 timestamp->channel = -1; in stm32_adc_chan_fw_init()
2313 timestamp->scan_index = scan_index; in stm32_adc_chan_fw_init()
2314 timestamp->scan_type.sign = 's'; in stm32_adc_chan_fw_init()
2315 timestamp->scan_type.realbits = 64; in stm32_adc_chan_fw_init()
2316 timestamp->scan_type.storagebits = 64; in stm32_adc_chan_fw_init()
2321 indio_dev->num_channels = scan_index; in stm32_adc_chan_fw_init()
2322 indio_dev->channels = channels; in stm32_adc_chan_fw_init()
2329 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_request() local
2333 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
2334 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
2335 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
2336 if (ret != -ENODEV) in stm32_adc_dma_request()
2341 adc->dma_chan = NULL; in stm32_adc_dma_request()
2345 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
2347 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
2348 if (!adc->rx_buf) { in stm32_adc_dma_request()
2349 ret = -ENOMEM; in stm32_adc_dma_request()
2355 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
2356 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
2359 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
2366 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
2367 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
2369 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
2377 struct device *dev = &pdev->dev; in stm32_adc_probe()
2379 struct stm32_adc *adc; in stm32_adc_probe() local
2383 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
2385 return -ENOMEM; in stm32_adc_probe()
2387 adc = iio_priv(indio_dev); in stm32_adc_probe()
2388 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
2389 spin_lock_init(&adc->lock); in stm32_adc_probe()
2390 init_completion(&adc->completion); in stm32_adc_probe()
2391 adc->cfg = device_get_match_data(dev); in stm32_adc_probe()
2393 indio_dev->name = dev_name(&pdev->dev); in stm32_adc_probe()
2394 device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev)); in stm32_adc_probe()
2395 indio_dev->info = &stm32_adc_iio_info; in stm32_adc_probe()
2396 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; in stm32_adc_probe()
2400 ret = device_property_read_u32(dev, "reg", &adc->offset); in stm32_adc_probe()
2402 dev_err(&pdev->dev, "missing reg property\n"); in stm32_adc_probe()
2403 return -EINVAL; in stm32_adc_probe()
2406 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
2407 if (adc->irq < 0) in stm32_adc_probe()
2408 return adc->irq; in stm32_adc_probe()
2410 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
2412 0, pdev->name, indio_dev); in stm32_adc_probe()
2414 dev_err(&pdev->dev, "failed to request IRQ\n"); in stm32_adc_probe()
2418 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
2419 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
2420 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
2421 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
2422 adc->clk = NULL; in stm32_adc_probe()
2424 dev_err(&pdev->dev, "Can't get clock\n"); in stm32_adc_probe()
2437 if (!adc->dma_chan) { in stm32_adc_probe()
2454 dev_err(&pdev->dev, "buffer setup failed\n"); in stm32_adc_probe()
2458 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
2471 dev_err(&pdev->dev, "iio dev register failed\n"); in stm32_adc_probe()
2493 if (adc->dma_chan) { in stm32_adc_probe()
2494 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
2496 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
2497 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2506 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_remove() local
2508 pm_runtime_get_sync(&pdev->dev); in stm32_adc_remove()
2511 stm32_adc_hw_stop(&pdev->dev); in stm32_adc_remove()
2512 pm_runtime_disable(&pdev->dev); in stm32_adc_remove()
2513 pm_runtime_set_suspended(&pdev->dev); in stm32_adc_remove()
2514 pm_runtime_put_noidle(&pdev->dev); in stm32_adc_remove()
2516 if (adc->dma_chan) { in stm32_adc_remove()
2517 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2519 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2520 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2547 indio_dev->active_scan_mask); in stm32_adc_resume()
2637 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2638 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2639 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2640 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg },
2649 .name = "stm32-adc",
2657 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2659 MODULE_ALIAS("platform:stm32-adc");