Lines Matching full:adc
3 * This file is part of STM32 ADC driver
32 #include "stm32-adc-core.h"
37 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
95 * struct stm32_adc_ic - ADC internal channels
113 * struct stm32_adc_trig_info - ADC trigger info
123 * struct stm32_adc_calib - optional adc calibration data
133 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
145 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data
213 * @smp_cycles: programmable sampling time (ADC clock cycles)
237 * struct stm32_adc - private data of each ADC IIO instance
238 * @common: reference to ADC block common data
239 * @offset: ADC instance register offset in ADC block
243 * @clk: clock for this adc instance
244 * @irq: interrupt for this adc instance
300 * struct stm32_adc_info - stm32 ADC, per instance config data
433 /* STM32F4 programmable sampling time (ADC clock cycles) */
527 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
548 /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */
594 * STM32 ADC registers access routines
595 * @adc: stm32 adc instance
596 * @reg: reg offset in adc instance
601 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) in stm32_adc_readl() argument
603 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
606 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
612 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) in stm32_adc_readw() argument
614 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
617 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) in stm32_adc_writel() argument
619 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
622 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits() argument
626 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
627 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); in stm32_adc_set_bits()
628 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
631 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits_common() argument
633 spin_lock(&adc->common->lock); in stm32_adc_set_bits_common()
634 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, in stm32_adc_set_bits_common()
635 adc->common->base + reg); in stm32_adc_set_bits_common()
636 spin_unlock(&adc->common->lock); in stm32_adc_set_bits_common()
639 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits() argument
643 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
644 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); in stm32_adc_clr_bits()
645 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
648 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits_common() argument
650 spin_lock(&adc->common->lock); in stm32_adc_clr_bits_common()
651 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, in stm32_adc_clr_bits_common()
652 adc->common->base + reg); in stm32_adc_clr_bits_common()
653 spin_unlock(&adc->common->lock); in stm32_adc_clr_bits_common()
658 * @adc: stm32 adc instance
660 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) in stm32_adc_conv_irq_enable() argument
662 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
663 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
668 * @adc: stm32 adc instance
670 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) in stm32_adc_conv_irq_disable() argument
672 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
673 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
676 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) in stm32_adc_ovr_irq_enable() argument
678 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
679 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
682 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) in stm32_adc_ovr_irq_disable() argument
684 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
685 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
688 static void stm32_adc_set_res(struct stm32_adc *adc) in stm32_adc_set_res() argument
690 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
693 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
694 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
695 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
701 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_stop() local
703 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
704 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
706 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
714 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_start() local
717 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
721 stm32_adc_set_res(adc); in stm32_adc_hw_start()
723 if (adc->cfg->prepare) { in stm32_adc_hw_start()
724 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
732 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
739 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_int_ch_enable() local
743 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_enable()
749 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_enable()
750 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_enable()
754 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_enable()
755 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_enable()
759 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_enable()
760 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_enable()
764 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_enable()
765 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_enable()
769 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_enable()
770 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_enable()
776 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) in stm32_adc_int_ch_disable() argument
781 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) in stm32_adc_int_ch_disable()
786 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, in stm32_adc_int_ch_disable()
787 adc->cfg->regs->or_vddcore.mask); in stm32_adc_int_ch_disable()
790 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, in stm32_adc_int_ch_disable()
791 adc->cfg->regs->or_vddcpu.mask); in stm32_adc_int_ch_disable()
794 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, in stm32_adc_int_ch_disable()
795 adc->cfg->regs->or_vddq_ddr.mask); in stm32_adc_int_ch_disable()
798 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, in stm32_adc_int_ch_disable()
799 adc->cfg->regs->ccr_vref.mask); in stm32_adc_int_ch_disable()
802 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, in stm32_adc_int_ch_disable()
803 adc->cfg->regs->ccr_vbat.mask); in stm32_adc_int_ch_disable()
816 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
821 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_start_conv() local
823 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_start_conv()
826 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_start_conv()
829 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); in stm32f4_adc_start_conv()
835 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) in stm32f4_adc_start_conv()
836 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); in stm32f4_adc_start_conv()
841 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_stop_conv() local
843 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); in stm32f4_adc_stop_conv()
844 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); in stm32f4_adc_stop_conv()
846 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_stop_conv()
847 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_stop_conv()
853 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_irq_clear() local
855 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
860 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_start_conv() local
870 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
871 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); in stm32h7_adc_start_conv()
873 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); in stm32h7_adc_start_conv()
874 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
876 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32h7_adc_start_conv()
881 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_stop_conv() local
885 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); in stm32h7_adc_stop_conv()
894 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); in stm32h7_adc_stop_conv()
899 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_irq_clear() local
901 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
906 struct stm32_adc *adc = iio_priv(indio_dev); in stm32mp13_adc_start_conv() local
909 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, in stm32mp13_adc_start_conv()
912 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32mp13_adc_start_conv()
917 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_set_ovs() local
921 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); in stm32h7_adc_set_ovs()
937 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); in stm32h7_adc_set_ovs()
942 struct stm32_adc *adc = iio_priv(indio_dev); in stm32mp13_adc_set_ovs() local
946 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); in stm32mp13_adc_set_ovs()
962 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); in stm32mp13_adc_set_ovs()
967 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_exit_pwr_down() local
971 /* Exit deep power down, then enable ADC voltage regulator */ in stm32h7_adc_exit_pwr_down()
972 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
973 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); in stm32h7_adc_exit_pwr_down()
975 if (adc->cfg->has_boostmode && in stm32h7_adc_exit_pwr_down()
976 adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
977 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_exit_pwr_down()
980 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
989 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
996 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) in stm32h7_adc_enter_pwr_down() argument
998 if (adc->cfg->has_boostmode) in stm32h7_adc_enter_pwr_down()
999 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_enter_pwr_down()
1001 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ in stm32h7_adc_enter_pwr_down()
1002 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_enter_pwr_down()
1007 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_enable() local
1011 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); in stm32h7_adc_enable()
1013 /* Poll for ADRDY to be set (after adc startup time) */ in stm32h7_adc_enable()
1018 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_enable()
1019 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
1022 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); in stm32h7_adc_enable()
1030 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_disable() local
1034 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) in stm32h7_adc_disable()
1037 /* Disable ADC and wait until it's effectively disabled */ in stm32h7_adc_disable()
1038 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_disable()
1049 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
1053 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_read_selfcalib() local
1061 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_read_selfcalib()
1072 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_read_selfcalib()
1073 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
1074 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
1078 adc->cal.lincal_saved = true; in stm32h7_adc_read_selfcalib()
1086 * Note: ADC must be enabled, with no on-going conversions.
1090 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_restore_selfcalib() local
1101 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
1102 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); in stm32h7_adc_restore_selfcalib()
1103 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1119 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
1127 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_restore_selfcalib()
1128 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
1140 * Fixed timeout value for ADC calibration.
1145 * - 131,072 ADC clock cycle for the linear calibration
1146 * - 20 ADC clock cycle for the offset calibration
1153 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
1156 * Note: Must be called once ADC is out of power down.
1163 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_selfcalib() local
1168 if (adc->cfg->has_linearcal && do_lincal) in stm32h7_adc_selfcalib()
1170 /* ADC must be disabled for calibration */ in stm32h7_adc_selfcalib()
1178 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1181 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1196 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1197 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
1208 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); in stm32h7_adc_selfcalib()
1223 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_check_selfcalib() local
1226 if (adc->cal.lincal_saved) in stm32h7_adc_check_selfcalib()
1230 * Check if linear calibration factors are available in ADC registers, in stm32h7_adc_check_selfcalib()
1233 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK; in stm32h7_adc_check_selfcalib()
1241 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
1244 * Configure channels as single ended or differential before enabling ADC.
1245 * Enable ADC.
1253 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_prepare() local
1261 if (adc->cfg->has_linearcal) in stm32h7_adc_prepare()
1271 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); in stm32h7_adc_prepare()
1277 if (adc->cfg->has_linearcal) { in stm32h7_adc_prepare()
1278 if (!adc->cal.lincal_saved) in stm32h7_adc_prepare()
1287 if (adc->cfg->has_presel) in stm32h7_adc_prepare()
1288 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
1295 stm32_adc_int_ch_disable(adc); in stm32h7_adc_prepare()
1297 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_prepare()
1304 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_unprepare() local
1306 if (adc->cfg->has_presel) in stm32h7_adc_unprepare()
1307 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); in stm32h7_adc_unprepare()
1309 stm32_adc_int_ch_disable(adc); in stm32h7_adc_unprepare()
1310 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_unprepare()
1320 * Configure ADC scan sequence based on selected channels in scan_mask.
1327 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_conf_scan_seq() local
1328 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1334 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1335 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1350 val = stm32_adc_readl(adc, sqr[i].reg); in stm32_adc_conf_scan_seq()
1353 stm32_adc_writel(adc, sqr[i].reg, val); in stm32_adc_conf_scan_seq()
1360 val = stm32_adc_readl(adc, sqr[0].reg); in stm32_adc_conf_scan_seq()
1363 stm32_adc_writel(adc, sqr[0].reg, val); in stm32_adc_conf_scan_seq()
1378 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_extsel() local
1382 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1389 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1390 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1409 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig() local
1421 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1424 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1425 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1426 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1427 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1428 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1429 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1430 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1439 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig_pol() local
1441 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1449 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_pol() local
1451 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1481 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_single_conv() local
1483 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1488 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1490 adc->bufi = 0; in stm32_adc_single_conv()
1497 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1498 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1501 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1504 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1507 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1510 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1512 stm32_adc_conv_irq_enable(adc); in stm32_adc_single_conv()
1514 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1517 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1523 *res = adc->buffer[0]; in stm32_adc_single_conv()
1527 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1529 stm32_adc_conv_irq_disable(adc); in stm32_adc_single_conv()
1541 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_write_raw() local
1543 int nb = adc->cfg->adc_info->num_ovs; in stm32_adc_write_raw()
1553 if (adc->cfg->adc_info->oversampling[idx] == val) in stm32_adc_write_raw()
1565 adc->cfg->set_ovs(indio_dev, idx); in stm32_adc_write_raw()
1570 adc->ovs_idx = idx; in stm32_adc_write_raw()
1585 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_avail() local
1590 *length = adc->cfg->adc_info->num_ovs; in stm32_adc_read_avail()
1591 *vals = adc->cfg->adc_info->oversampling; in stm32_adc_read_avail()
1602 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_raw() local
1616 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; in stm32_adc_read_raw()
1623 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1626 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1640 *val = adc->cfg->adc_info->oversampling[adc->ovs_idx]; in stm32_adc_read_raw()
1650 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_irq_clear() local
1652 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1658 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_threaded_isr() local
1659 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1660 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1666 * This requires to stop ADC first. OVR bit state in ISR, in stm32_adc_threaded_isr()
1669 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1681 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_isr() local
1682 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1683 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1693 stm32_adc_ovr_irq_disable(adc); in stm32_adc_isr()
1694 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1700 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1702 adc->bufi++; in stm32_adc_isr()
1703 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1704 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1708 complete(&adc->completion); in stm32_adc_isr()
1717 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1721 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1732 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_watermark() local
1743 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1751 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_update_scan_mode() local
1759 adc->num_conv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev)); in stm32_adc_update_scan_mode()
1787 * To read a value from an ADC register:
1788 * echo [ADC reg offset] > direct_reg_access
1791 * To write a value in a ADC register:
1798 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_reg_access() local
1807 stm32_adc_writel(adc, reg, writeval); in stm32_adc_debugfs_reg_access()
1809 *readval = stm32_adc_readl(adc, reg); in stm32_adc_debugfs_reg_access()
1828 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) in stm32_adc_dma_residue() argument
1833 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1834 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1838 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1842 if (i >= adc->bufi) in stm32_adc_dma_residue()
1843 size = i - adc->bufi; in stm32_adc_dma_residue()
1845 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1856 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_buffer_done() local
1857 int residue = stm32_adc_dma_residue(adc); in stm32_adc_dma_buffer_done()
1868 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1871 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1876 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1877 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1878 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1884 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_start() local
1889 if (!adc->dma_chan) in stm32_adc_dma_start()
1893 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1896 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1897 adc->rx_dma_buf, in stm32_adc_dma_start()
1898 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1910 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1915 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1922 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_postenable() local
1942 /* Reset adc buffer index */ in stm32_adc_buffer_postenable()
1943 adc->bufi = 0; in stm32_adc_buffer_postenable()
1945 stm32_adc_ovr_irq_enable(adc); in stm32_adc_buffer_postenable()
1947 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1948 stm32_adc_conv_irq_enable(adc); in stm32_adc_buffer_postenable()
1950 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1965 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_predisable() local
1968 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1969 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1970 stm32_adc_conv_irq_disable(adc); in stm32_adc_buffer_predisable()
1972 stm32_adc_ovr_irq_disable(adc); in stm32_adc_buffer_predisable()
1974 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1975 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1995 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_trigger_handler() local
1997 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
2000 adc->bufi = 0; in stm32_adc_trigger_handler()
2001 iio_push_to_buffers_with_ts(indio_dev, adc->buffer, sizeof(adc->buffer), in stm32_adc_trigger_handler()
2006 stm32_adc_conv_irq_enable(adc); in stm32_adc_trigger_handler()
2024 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_init() local
2026 struct stm32_adc_calib *cal = &adc->cal; in stm32_adc_debugfs_init()
2030 if (!adc->cfg->has_linearcal) in stm32_adc_debugfs_init()
2042 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_fw_get_resolution() local
2047 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_fw_get_resolution()
2049 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_fw_get_resolution()
2050 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_fw_get_resolution()
2052 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_fw_get_resolution()
2058 adc->res = i; in stm32_adc_fw_get_resolution()
2063 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) in stm32_adc_smpr_init() argument
2065 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
2074 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE) in stm32_adc_smpr_init()
2075 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]); in stm32_adc_smpr_init()
2077 /* Determine sampling time (ADC clock cycles) */ in stm32_adc_smpr_init()
2078 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
2080 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
2086 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
2093 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_init_one() local
2094 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
2108 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) in stm32_adc_chan_init_one()
2114 if (adc->cfg->has_oversampling) { in stm32_adc_chan_init_one()
2119 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
2124 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
2127 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; in stm32_adc_chan_init_one()
2129 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
2133 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) in stm32_adc_get_legacy_chan_count() argument
2136 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_get_legacy_chan_count()
2141 ret = device_property_count_u32(dev, "st,adc-channels"); in stm32_adc_get_legacy_chan_count()
2143 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_get_legacy_chan_count()
2150 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret in stm32_adc_get_legacy_chan_count()
2153 ret = device_property_count_u32(dev, "st,adc-diff-channels"); in stm32_adc_get_legacy_chan_count()
2157 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_get_legacy_chan_count()
2160 adc->num_diff = ret; in stm32_adc_get_legacy_chan_count()
2166 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); in stm32_adc_get_legacy_chan_count()
2167 if (adc->nsmps > 1 && adc->nsmps != num_channels) { in stm32_adc_get_legacy_chan_count()
2176 struct stm32_adc *adc, in stm32_adc_legacy_chan_init() argument
2180 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_legacy_chan_init()
2183 u32 num_diff = adc->num_diff; in stm32_adc_legacy_chan_init()
2190 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", in stm32_adc_legacy_chan_init()
2212 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); in stm32_adc_legacy_chan_init()
2214 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret); in stm32_adc_legacy_chan_init()
2239 if (adc->nsmps > 0) { in stm32_adc_legacy_chan_init()
2241 smps, adc->nsmps); in stm32_adc_legacy_chan_init()
2254 if (i < adc->nsmps) in stm32_adc_legacy_chan_init()
2258 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_legacy_chan_init()
2267 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_populate_int_ch() local
2276 if (!adc->cfg->regs->or_vddcore.reg) in stm32_adc_populate_int_ch()
2281 if (!adc->cfg->regs->or_vddcpu.reg) in stm32_adc_populate_int_ch()
2286 if (!adc->cfg->regs->or_vddq_ddr.reg) in stm32_adc_populate_int_ch()
2291 if (!adc->cfg->regs->ccr_vref.reg) in stm32_adc_populate_int_ch()
2296 if (!adc->cfg->regs->ccr_vbat.reg) in stm32_adc_populate_int_ch()
2303 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2320 adc->int_ch[i] = chan; in stm32_adc_populate_int_ch()
2321 adc->vrefint.vrefint_cal = vrefint; in stm32_adc_populate_int_ch()
2329 struct stm32_adc *adc, in stm32_adc_generic_chan_init() argument
2332 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_generic_chan_init()
2353 strscpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); in stm32_adc_generic_chan_init()
2391 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); in stm32_adc_generic_chan_init()
2393 stm32_adc_smpr_init(adc, vin[1], val); in stm32_adc_generic_chan_init()
2403 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_fw_init() local
2404 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_fw_init()
2410 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; in stm32_adc_chan_fw_init()
2417 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); in stm32_adc_chan_fw_init()
2443 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, in stm32_adc_chan_fw_init()
2446 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); in stm32_adc_chan_fw_init()
2472 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_request() local
2476 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
2477 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
2478 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
2484 adc->dma_chan = NULL; in stm32_adc_dma_request()
2488 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
2490 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
2491 if (!adc->rx_buf) { in stm32_adc_dma_request()
2498 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
2499 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
2502 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
2509 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
2510 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
2512 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
2522 struct stm32_adc *adc; in stm32_adc_probe() local
2526 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
2530 adc = iio_priv(indio_dev); in stm32_adc_probe()
2531 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
2532 spin_lock_init(&adc->lock); in stm32_adc_probe()
2533 init_completion(&adc->completion); in stm32_adc_probe()
2534 adc->cfg = device_get_match_data(dev); in stm32_adc_probe()
2543 ret = device_property_read_u32(dev, "reg", &adc->offset); in stm32_adc_probe()
2549 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
2550 if (adc->irq < 0) in stm32_adc_probe()
2551 return adc->irq; in stm32_adc_probe()
2553 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
2561 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
2562 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
2563 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
2564 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
2565 adc->clk = NULL; in stm32_adc_probe()
2580 if (!adc->dma_chan) { in stm32_adc_probe()
2601 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
2636 if (adc->dma_chan) { in stm32_adc_probe()
2637 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
2639 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
2640 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2649 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_remove() local
2659 if (adc->dma_chan) { in stm32_adc_remove()
2660 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2662 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2663 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2786 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2787 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2788 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2789 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg },
2798 .name = "stm32-adc",
2806 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2808 MODULE_ALIAS("platform:stm32-adc");