1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas RZ/N1 ADC driver
5  * Copyright (C) 2025 Schneider-Electric
9  * The RZ/N1 ADC controller can handle channels from its internal ADC1 and/or
11  * of the related power supplies (AVDD and VREF) description in the device-tree.
53 #define RZN1_ADC_NO_CHANNEL	-1
101  * based on Vref connected on each ADC core.
125 	struct mutex lock; /* ADC lock */
135 	       rzn1_adc->regs + RZN1_ADC_CONFIG_REG);  in rzn1_adc_power()
138 	return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG,  in rzn1_adc_power()
156 	writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));  in rzn1_adc_vc_setup_conversion()
163 	val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);  in rzn1_adc_vc_start_conversion()
165 		return -EBUSY;  in rzn1_adc_vc_start_conversion()
167 	writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);  in rzn1_adc_vc_start_conversion()
174 	writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);  in rzn1_adc_vc_stop_conversion()
185 	 * When a VC is selected, it needs 20 ADC clocks to perform the  in rzn1_adc_vc_wait_conversion()
191 	 * In that case, the conversion is performed in 16 * 20 ADC clocks.  in rzn1_adc_vc_wait_conversion()
193 	 * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst  in rzn1_adc_vc_wait_conversion()
200 	ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,  in rzn1_adc_vc_wait_conversion()
207 		data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));  in rzn1_adc_vc_wait_conversion()
212 		data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));  in rzn1_adc_vc_wait_conversion()
228 	 * The RZ/N1 ADC VC controller can handle on a single VC chan one  in rzn1_adc_read_raw_ch()
231 	 * Even if IIO chans are mapped 1:1 to ADC core chans and so uses only  in rzn1_adc_read_raw_ch()
246 		adc2_ch = chan - 8;  in rzn1_adc_read_raw_ch()
249 		return -EINVAL;  in rzn1_adc_read_raw_ch()
252 	ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev);  in rzn1_adc_read_raw_ch()
257 	scoped_guard(mutex, &rzn1_adc->lock) {  in rzn1_adc_read_raw_ch()
281 		return rzn1_adc->adc1_vref_mV;  in rzn1_adc_get_vref_mV()
285 		return rzn1_adc->adc2_vref_mV;  in rzn1_adc_get_vref_mV()
287 	return -EINVAL;  in rzn1_adc_get_vref_mV()
298 		ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val);  in rzn1_adc_read_raw()
304 		ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel);  in rzn1_adc_read_raw()
312 		return -EINVAL;  in rzn1_adc_read_raw()
324 	 * When an ADC core is not used, its related vref_mV is set to a  in rzn1_adc_set_iio_dev_channels()
328 	if (rzn1_adc->adc1_vref_mV >= 0) {  in rzn1_adc_set_iio_dev_channels()
329 		if (rzn1_adc->adc2_vref_mV >= 0) {  in rzn1_adc_set_iio_dev_channels()
330 			indio_dev->channels = rzn1_adc1_adc2_channels;  in rzn1_adc_set_iio_dev_channels()
331 			indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_adc2_channels);  in rzn1_adc_set_iio_dev_channels()
333 			indio_dev->channels = rzn1_adc1_channels;  in rzn1_adc_set_iio_dev_channels()
334 			indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_channels);  in rzn1_adc_set_iio_dev_channels()
339 	if (rzn1_adc->adc2_vref_mV >= 0) {  in rzn1_adc_set_iio_dev_channels()
340 		indio_dev->channels = rzn1_adc2_channels;  in rzn1_adc_set_iio_dev_channels()
341 		indio_dev->num_channels = ARRAY_SIZE(rzn1_adc2_channels);  in rzn1_adc_set_iio_dev_channels()
345 	return dev_err_probe(rzn1_adc->dev, -ENODEV,  in rzn1_adc_set_iio_dev_channels()
346 			     "Failed to set IIO channels, no ADC core used\n");  in rzn1_adc_set_iio_dev_channels()
353 	struct device *dev = rzn1_adc->dev;  in rzn1_adc_core_get_regulators()
357 	 * For a given ADC core (ADC1 or ADC2), both regulators (AVDD and VREF)  in rzn1_adc_core_get_regulators()
358 	 * must be available in order to have the ADC core used.  in rzn1_adc_core_get_regulators()
361 	 * ADC core. If both regulators are available, the ADC core is used.  in rzn1_adc_core_get_regulators()
362 	 * Otherwise, the ADC core is not used.  in rzn1_adc_core_get_regulators()
364 	 * The adc_vref_mV value is set to a negative error code (-ENODEV) when  in rzn1_adc_core_get_regulators()
365 	 * the ADC core is not used. Otherwise it is set to the VRef mV value.  in rzn1_adc_core_get_regulators()
368 	*adc_vref_mV = -ENODEV;  in rzn1_adc_core_get_regulators()
371 	if (ret == -ENODEV)  in rzn1_adc_core_get_regulators()
378 	if (ret == -ENODEV)  in rzn1_adc_core_get_regulators()
387 	 * positive, also signals that the ADC is used.  in rzn1_adc_core_get_regulators()
396 	struct device *dev = &pdev->dev;  in rzn1_adc_probe()
404 		return -ENOMEM;  in rzn1_adc_probe()
407 	rzn1_adc->dev = dev;  in rzn1_adc_probe()
409 	ret = devm_mutex_init(dev, &rzn1_adc->lock);  in rzn1_adc_probe()
413 	rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0);  in rzn1_adc_probe()
414 	if (IS_ERR(rzn1_adc->regs))  in rzn1_adc_probe()
415 		return PTR_ERR(rzn1_adc->regs);  in rzn1_adc_probe()
421 	clk = devm_clk_get_enabled(dev, "adc");  in rzn1_adc_probe()
423 		return dev_err_probe(dev, PTR_ERR(clk), "Failed to get adc clk\n");  in rzn1_adc_probe()
425 	ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV,  in rzn1_adc_probe()
426 					   "adc1-avdd", "adc1-vref");  in rzn1_adc_probe()
430 	ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV,  in rzn1_adc_probe()
431 					   "adc2-avdd", "adc2-vref");  in rzn1_adc_probe()
437 	indio_dev->name = "rzn1-adc";  in rzn1_adc_probe()
438 	indio_dev->info = &rzn1_adc_info;  in rzn1_adc_probe()
439 	indio_dev->modes = INDIO_DIRECT_MODE;  in rzn1_adc_probe()
473 	{ .compatible = "renesas,rzn1-adc" },
481 		.name = "rzn1-adc",
489 MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver");