Lines Matching full:adc
3 * Freescale MXS LRADC ADC driver
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_single() local
135 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_read_single()
147 reinit_completion(&adc->completion); in mxs_lradc_adc_read_single()
156 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
157 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
160 if (test_bit(chan, &adc->is_divided)) in mxs_lradc_adc_read_single()
162 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
165 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
169 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
170 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
172 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single()
176 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
177 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
180 ret = wait_for_completion_killable_timeout(&adc->completion, HZ); in mxs_lradc_adc_read_single()
187 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; in mxs_lradc_adc_read_single()
192 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
220 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_raw() local
240 *val = adc->vref_mv[chan->channel]; in mxs_lradc_adc_read_raw()
242 test_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_read_raw()
248 * The calculated value from the ADC is in Kelvin, we in mxs_lradc_adc_read_raw()
272 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_write_raw() local
274 adc->scale_avail[chan->channel]; in mxs_lradc_adc_write_raw()
286 clear_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_write_raw()
291 set_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_write_raw()
318 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_show_scale_avail() local
323 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++) in mxs_lradc_adc_show_scale_avail()
325 adc->scale_avail[ch][i].integer, in mxs_lradc_adc_show_scale_avail()
326 adc->scale_avail[ch][i].nano); in mxs_lradc_adc_show_scale_avail()
385 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_handle_irq() local
386 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_handle_irq()
387 unsigned long reg = readl(adc->base + LRADC_CTRL1); in mxs_lradc_adc_handle_irq()
395 spin_lock_irqsave(&adc->lock, flags); in mxs_lradc_adc_handle_irq()
397 spin_unlock_irqrestore(&adc->lock, flags); in mxs_lradc_adc_handle_irq()
400 complete(&adc->completion); in mxs_lradc_adc_handle_irq()
404 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_handle_irq()
415 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_handler() local
421 adc->buffer[j] = readl(adc->base + LRADC_CH(j)); in mxs_lradc_adc_trigger_handler()
422 writel(chan_value, adc->base + LRADC_CH(j)); in mxs_lradc_adc_trigger_handler()
423 adc->buffer[j] &= LRADC_CH_VALUE_MASK; in mxs_lradc_adc_trigger_handler()
424 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; in mxs_lradc_adc_trigger_handler()
428 iio_push_to_buffers_with_ts(iio, adc->buffer, sizeof(adc->buffer), in mxs_lradc_adc_trigger_handler()
439 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_configure_trigger() local
442 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st)); in mxs_lradc_adc_configure_trigger()
455 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_init() local
462 trig->dev.parent = adc->dev; in mxs_lradc_adc_trigger_init()
470 adc->trig = trig; in mxs_lradc_adc_trigger_init()
477 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_remove() local
479 iio_trigger_unregister(adc->trig); in mxs_lradc_adc_trigger_remove()
484 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_buffer_preenable() local
485 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_buffer_preenable()
496 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
498 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
504 writel(chan_value, adc->base + LRADC_CH(ofs)); in mxs_lradc_adc_buffer_preenable()
510 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
511 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
512 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
513 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
515 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
522 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_buffer_postdisable() local
523 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_buffer_postdisable()
526 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
529 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
532 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
540 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_validate_scan_mask() local
541 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_validate_scan_mask()
664 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc) in mxs_lradc_adc_hw_init() argument
666 /* The ADC always uses DELAY CHANNEL 0. */ in mxs_lradc_adc_hw_init()
671 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ in mxs_lradc_adc_hw_init()
672 writel(adc_cfg, adc->base + LRADC_DELAY(0)); in mxs_lradc_adc_hw_init()
679 writel(0, adc->base + LRADC_CTRL2); in mxs_lradc_adc_hw_init()
682 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc) in mxs_lradc_adc_hw_stop() argument
684 writel(0, adc->base + LRADC_DELAY(0)); in mxs_lradc_adc_hw_stop()
691 struct mxs_lradc_adc *adc; in mxs_lradc_adc_probe() local
699 iio = devm_iio_device_alloc(dev, sizeof(*adc)); in mxs_lradc_adc_probe()
705 adc = iio_priv(iio); in mxs_lradc_adc_probe()
706 adc->lradc = lradc; in mxs_lradc_adc_probe()
707 adc->dev = dev; in mxs_lradc_adc_probe()
713 adc->base = devm_ioremap(dev, iores->start, resource_size(iores)); in mxs_lradc_adc_probe()
714 if (!adc->base) in mxs_lradc_adc_probe()
717 init_completion(&adc->completion); in mxs_lradc_adc_probe()
718 spin_lock_init(&adc->lock); in mxs_lradc_adc_probe()
739 ret = stmp_reset_block(adc->base); in mxs_lradc_adc_probe()
766 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; in mxs_lradc_adc_probe()
768 /* Populate available ADC input ranges */ in mxs_lradc_adc_probe()
770 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) { in mxs_lradc_adc_probe()
780 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >> in mxs_lradc_adc_probe()
782 adc->scale_avail[i][s].nano = in mxs_lradc_adc_probe()
784 adc->scale_avail[i][s].integer = scale_uv; in mxs_lradc_adc_probe()
789 mxs_lradc_adc_hw_init(adc); in mxs_lradc_adc_probe()
801 mxs_lradc_adc_hw_stop(adc); in mxs_lradc_adc_probe()
811 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_remove() local
814 mxs_lradc_adc_hw_stop(adc); in mxs_lradc_adc_remove()
821 .name = "mxs-lradc-adc",
829 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
831 MODULE_ALIAS("platform:mxs-lradc-adc");