1 // SPDX-License-Identifier: GPL-2.0
31 #define MT6360_ADCEN_MASK	BIT(15)
61 	/* Due to only one set of ADC control, this lock is used to prevent the race condition */
69 	u8 rpt[3];  in mt6360_adc_read_channel()  local
74 	mutex_lock(&mad->adc_lock);  in mt6360_adc_read_channel()
76 	/* Select the preferred ADC channel */  in mt6360_adc_read_channel()
77 	ret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,  in mt6360_adc_read_channel()
82 	adc_enable = cpu_to_be16(MT6360_ADCEN_MASK | BIT(channel));  in mt6360_adc_read_channel()
83 	ret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));  in mt6360_adc_read_channel()
87 	predict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS);  in mt6360_adc_read_channel()
95 		ret = -ERESTARTSYS;  in mt6360_adc_read_channel()
101 		ret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt));  in mt6360_adc_read_channel()
106 		 * There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in  in mt6360_adc_read_channel()
107 		 * background, and ADC samples are taken on a fixed frequency no matter read the  in mt6360_adc_read_channel()
109 		 * To avoid conflict, We set minimum time threshold after enable ADC and  in mt6360_adc_read_channel()
111 		 * The worst case is run the same ADC twice and background function is also running,  in mt6360_adc_read_channel()
112 		 * ADC conversion sequence is desire channel before start ADC, background ADC,  in mt6360_adc_read_channel()
113 		 * desire channel after start ADC.  in mt6360_adc_read_channel()
116 		if ((rpt[0] & MT6360_RPTCH_MASK) == channel)  in mt6360_adc_read_channel()
120 			ret = -ETIMEDOUT;  in mt6360_adc_read_channel()
127 	*val = rpt[1] << 8 | rpt[2];  in mt6360_adc_read_channel()
131 	/* Only keep ADC enable */  in mt6360_adc_read_channel()
133 	regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));  in mt6360_adc_read_channel()
134 	mad->last_off_timestamps[channel] = ktime_get();  in mt6360_adc_read_channel()
136 	regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,  in mt6360_adc_read_channel()
139 	mutex_unlock(&mad->adc_lock);  in mt6360_adc_read_channel()
169 			ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, &regval);  in mt6360_adc_read_scale()
185 	return -EINVAL;  in mt6360_adc_read_scale()
190 	*val = (channel == MT6360_CHAN_TEMP_JC) ? -80 : 0;  in mt6360_adc_read_offset()
201 		return mt6360_adc_read_channel(mad, chan->channel, val);  in mt6360_adc_read_raw()
203 		return mt6360_adc_read_scale(mad, chan->channel, val, val2);  in mt6360_adc_read_raw()
205 		return mt6360_adc_read_offset(mad, chan->channel, val);  in mt6360_adc_read_raw()
208 	return -EINVAL;  in mt6360_adc_read_raw()
219 	return snprintf(label, PAGE_SIZE, "%s\n", mt6360_channel_labels[chan->channel]);  in mt6360_adc_read_label()
238 	.indexed = 1,						\
239 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
240 				BIT(IIO_CHAN_INFO_SCALE) |	\
241 				BIT(IIO_CHAN_INFO_OFFSET),	\
262 	struct iio_dev *indio_dev = pf->indio_dev;  in mt6360_adc_trigger_handler()
268 	int i = 0, bit, val, ret;  in mt6360_adc_trigger_handler()  local
271 	iio_for_each_active_channel(indio_dev, bit) {  in mt6360_adc_trigger_handler()
272 		ret = mt6360_adc_read_channel(mad, bit, &val);  in mt6360_adc_trigger_handler()
274 			dev_warn(&indio_dev->dev, "Failed to get channel %d conversion val\n", bit);  in mt6360_adc_trigger_handler()
282 	iio_trigger_notify_done(indio_dev->trig);  in mt6360_adc_trigger_handler()
293 	/* Clear ADC idle wait time to 0 */  in mt6360_adc_reset()
294 	ret = regmap_write(info->regmap, MT6360_REG_PMUADCIDLET, 0);  in mt6360_adc_reset()
298 	/* Only keep ADC enable, but keep all channels off */  in mt6360_adc_reset()
300 	ret = regmap_raw_write(info->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));  in mt6360_adc_reset()
307 		info->last_off_timestamps[i] = all_off_time;  in mt6360_adc_reset()
319 	regmap = dev_get_regmap(pdev->dev.parent, NULL);  in mt6360_adc_probe()
321 		dev_err(&pdev->dev, "Failed to get parent regmap\n");  in mt6360_adc_probe()
322 		return -ENODEV;  in mt6360_adc_probe()
325 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*mad));  in mt6360_adc_probe()
327 		return -ENOMEM;  in mt6360_adc_probe()
330 	mad->dev = &pdev->dev;  in mt6360_adc_probe()
331 	mad->regmap = regmap;  in mt6360_adc_probe()
332 	mutex_init(&mad->adc_lock);  in mt6360_adc_probe()
336 		dev_err(&pdev->dev, "Failed to reset adc\n");  in mt6360_adc_probe()
340 	indio_dev->name = dev_name(&pdev->dev);  in mt6360_adc_probe()
341 	indio_dev->info = &mt6360_adc_iio_info;  in mt6360_adc_probe()
342 	indio_dev->modes = INDIO_DIRECT_MODE;  in mt6360_adc_probe()
343 	indio_dev->channels = mt6360_adc_channels;  in mt6360_adc_probe()
344 	indio_dev->num_channels = ARRAY_SIZE(mt6360_adc_channels);  in mt6360_adc_probe()
346 	ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, NULL,  in mt6360_adc_probe()
349 		dev_err(&pdev->dev, "Failed to allocate iio trigger buffer\n");  in mt6360_adc_probe()
353 	return devm_iio_device_register(&pdev->dev, indio_dev);  in mt6360_adc_probe()
357 	{ .compatible = "mediatek,mt6360-adc", },
364 		.name = "mt6360-adc",
372 MODULE_DESCRIPTION("MT6360 ADC Driver");