Lines Matching +full:8 +full:- +full:15
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/iio/adc/mediatek,mt6357-auxadc.h>
26 #include <dt-bindings/iio/adc/mediatek,mt6358-auxadc.h>
27 #include <dt-bindings/iio/adc/mediatek,mt6359-auxadc.h>
28 #include <dt-bindings/iio/adc/mediatek,mt6363-auxadc.h>
38 #define PMIC_AUXADC_RDY_BIT BIT(15)
44 #define MT6358_IMP0_IRQ_RDY BIT(8)
45 #define MT6358_IMP1_AUTOREPEAT_EN BIT(15)
48 #define MT6359_IMP1_IRQ_RDY BIT(15)
103 * struct mt6359_auxadc - Main driver structure
119 * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data
143 * struct mtk_pmic_auxadc_info - PMIC specific chip info
189 -1, 0, 0, _samples, _rnum, _rdiv)
209 MTK_PMIC_IIO_CHAN(MT6357, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
216 MTK_PMIC_IIO_CHAN(MT6357, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
217 MTK_PMIC_IIO_CHAN(MT6357, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
218 MTK_PMIC_IIO_CHAN(MT6357, dcxo_temp, DCXO_TEMP, 36, 15, IIO_TEMP),
223 MTK_PMIC_IIO_CHAN(MT6357, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
227 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
228 MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
229 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
230 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
231 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
232 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
233 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
234 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
235 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
236 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
237 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
238 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
241 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
255 MTK_PMIC_IIO_CHAN(MT6358, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
261 MTK_PMIC_IIO_CHAN(MT6358, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
262 MTK_PMIC_IIO_CHAN(MT6358, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
263 MTK_PMIC_IIO_CHAN(MT6358, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP),
270 MTK_PMIC_IIO_CHAN(MT6358, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
274 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
275 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
276 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
277 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
278 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
279 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3, 2),
280 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
281 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
282 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
283 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
284 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
285 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
286 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
289 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2),
303 MTK_PMIC_IIO_CHAN(MT6359, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
308 MTK_PMIC_IIO_CHAN(MT6359, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
309 MTK_PMIC_IIO_CHAN(MT6359, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
310 MTK_PMIC_IIO_CHAN(MT6359, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP),
317 MTK_PMIC_IIO_CHAN(MT6359, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
318 MTK_PMIC_IIO_CHAN(MT6359, batt_i, IBAT, 0, 15, IIO_CURRENT),
322 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
323 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
324 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
325 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, 1, 1),
326 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2),
327 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1),
328 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1),
329 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15, 16, 1, 1),
330 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
331 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
332 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
333 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
336 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
337 MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
353 MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
357 MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE),
364 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE),
365 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE),
366 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE),
367 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE),
368 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE),
369 MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE),
370 MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE),
374 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64, 4, 1),
375 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
376 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2),
377 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
378 MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64, 3, 1),
379 MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2),
380 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
381 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
382 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
385 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
388 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
391 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
394 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
397 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
400 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
403 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
423 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE),
424 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE),
425 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE),
426 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE),
427 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE),
431 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
432 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
433 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
434 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
437 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
440 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
443 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
446 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
449 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
455 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6358_stop_imp_conv()
456 struct regmap *regmap = adc_dev->regmap; in mt6358_stop_imp_conv()
458 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR); in mt6358_stop_imp_conv()
459 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR); in mt6358_stop_imp_conv()
460 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN); in mt6358_stop_imp_conv()
461 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); in mt6358_stop_imp_conv()
466 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6358_start_imp_conv()
467 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; in mt6358_start_imp_conv()
468 struct regmap *regmap = adc_dev->regmap; in mt6358_start_imp_conv()
472 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN); in mt6358_start_imp_conv()
473 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN); in mt6358_start_imp_conv()
475 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], in mt6358_start_imp_conv()
476 val, val & desc->rdy_mask, in mt6358_start_imp_conv()
489 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6358_read_imp()
490 struct regmap *regmap = adc_dev->regmap; in mt6358_read_imp()
491 u16 reg_adc0 = cinfo->regs[PMIC_AUXADC_ADC0]; in mt6358_read_imp()
500 regmap_read(regmap, reg_adc0 + (cinfo->imp_adc_num << 1), &val_v); in mt6358_read_imp()
515 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6359_read_imp()
516 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; in mt6359_read_imp()
517 struct regmap *regmap = adc_dev->regmap; in mt6359_read_imp()
522 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); in mt6359_read_imp()
523 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], in mt6359_read_imp()
524 val, val & desc->rdy_mask, in mt6359_read_imp()
528 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], 0); in mt6359_read_imp()
535 ret = regmap_read(regmap, cinfo->regs[PMIC_AUXADC_IMP3], &val_v); in mt6359_read_imp()
539 ret = regmap_read(regmap, cinfo->regs[PMIC_FGADC_R_CON0], &val_i); in mt6359_read_imp()
608 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6359_auxadc_reset()
609 struct regmap *regmap = adc_dev->regmap; in mt6359_auxadc_reset()
612 if (cinfo->no_reset) in mt6359_auxadc_reset()
616 if (cinfo->sec_unlock_key) in mt6359_auxadc_reset()
617 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], cinfo->sec_unlock_key); in mt6359_auxadc_reset()
620 regmap_set_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL); in mt6359_auxadc_reset()
622 /* De-assert ADC reset. No wait required, as pwrap takes care of that for us. */ in mt6359_auxadc_reset()
623 regmap_clear_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL); in mt6359_auxadc_reset()
626 if (cinfo->sec_unlock_key) in mt6359_auxadc_reset()
627 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], 0); in mt6359_auxadc_reset()
631 * mt6359_auxadc_sample_adc_val() - Start ADC channel sampling and read value
649 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6359_auxadc_sample_adc_val()
650 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; in mt6359_auxadc_sample_adc_val()
651 struct regmap *regmap = adc_dev->regmap; in mt6359_auxadc_sample_adc_val()
656 ret = regmap_write(regmap, cinfo->regs[desc->req_idx], desc->req_mask); in mt6359_auxadc_sample_adc_val()
661 fsleep(desc->num_samples * AUXADC_AVG_TIME_US); in mt6359_auxadc_sample_adc_val()
663 reg = cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1); in mt6359_auxadc_sample_adc_val()
669 * read is only 8 bits long: for this case, the check has to be done in mt6359_auxadc_sample_adc_val()
671 * shifted to the right by the same 8 bits. in mt6359_auxadc_sample_adc_val()
673 if (cinfo->is_spmi) { in mt6359_auxadc_sample_adc_val()
674 rdy_mask >>= 8; in mt6359_auxadc_sample_adc_val()
681 dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address); in mt6359_auxadc_sample_adc_val()
685 if (cinfo->is_spmi) { in mt6359_auxadc_sample_adc_val()
686 ret = regmap_read(regmap, reg - 1, &lval); in mt6359_auxadc_sample_adc_val()
690 val = (val << 8) | lval; in mt6359_auxadc_sample_adc_val()
700 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6359_auxadc_read_adc()
701 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; in mt6359_auxadc_read_adc()
702 struct regmap *regmap = adc_dev->regmap; in mt6359_auxadc_read_adc()
707 if (desc->ext_sel_idx >= 0) { in mt6359_auxadc_read_adc()
708 ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu); in mt6359_auxadc_read_adc()
709 ext_sel |= FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch); in mt6359_auxadc_read_adc()
711 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], in mt6359_auxadc_read_adc()
726 * read attempt will return -ETIMEDOUT and, for models that support it, in mt6359_auxadc_read_adc()
731 adc_stop_err = regmap_write(regmap, cinfo->regs[desc->req_idx], 0); in mt6359_auxadc_read_adc()
733 dev_warn(adc_dev->dev, "Could not stop the ADC: %d\n,", adc_stop_err); in mt6359_auxadc_read_adc()
734 adc_dev->timed_out = true; in mt6359_auxadc_read_adc()
742 if (desc->ext_sel_idx >= 0) { in mt6359_auxadc_read_adc()
745 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], in mt6359_auxadc_read_adc()
752 *out = val & GENMASK(chan->scan_type.realbits - 1, 0); in mt6359_auxadc_read_adc()
759 return sysfs_emit(label, "%s\n", chan->datasheet_name); in mt6359_auxadc_read_label()
767 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info; in mt6359_auxadc_read_raw()
768 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index]; in mt6359_auxadc_read_raw()
772 *val = desc->r_ratio.numerator * cinfo->vref_mV; in mt6359_auxadc_read_raw()
774 if (desc->r_ratio.denominator > 1) { in mt6359_auxadc_read_raw()
775 *val2 = desc->r_ratio.denominator; in mt6359_auxadc_read_raw()
782 scoped_guard(mutex, &adc_dev->lock) { in mt6359_auxadc_read_raw()
783 switch (chan->scan_index) { in mt6359_auxadc_read_raw()
785 if (!adc_dev->chip_info->read_imp) in mt6359_auxadc_read_raw()
786 return -EOPNOTSUPP; in mt6359_auxadc_read_raw()
788 ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); in mt6359_auxadc_read_raw()
791 if (!adc_dev->chip_info->read_imp) in mt6359_auxadc_read_raw()
792 return -EOPNOTSUPP; in mt6359_auxadc_read_raw()
794 ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); in mt6359_auxadc_read_raw()
807 if (ret == -ETIMEDOUT) { in mt6359_auxadc_read_raw()
808 if (adc_dev->timed_out) { in mt6359_auxadc_read_raw()
809 dev_warn(adc_dev->dev, "Resetting stuck ADC!\r\n"); in mt6359_auxadc_read_raw()
812 adc_dev->timed_out = true; in mt6359_auxadc_read_raw()
816 adc_dev->timed_out = false; in mt6359_auxadc_read_raw()
829 struct device *dev = &pdev->dev; in mt6359_auxadc_probe()
830 struct device *mfd_dev = dev->parent; in mt6359_auxadc_probe()
839 return -EINVAL; in mt6359_auxadc_probe()
845 * this driver: this_device->parent(mfd). in mt6359_auxadc_probe()
848 * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap) in mt6359_auxadc_probe()
850 if (chip_info->is_spmi) in mt6359_auxadc_probe()
853 regmap_dev = mfd_dev->parent; in mt6359_auxadc_probe()
859 return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n"); in mt6359_auxadc_probe()
863 return -ENOMEM; in mt6359_auxadc_probe()
866 adc_dev->regmap = regmap; in mt6359_auxadc_probe()
867 adc_dev->dev = dev; in mt6359_auxadc_probe()
868 adc_dev->chip_info = chip_info; in mt6359_auxadc_probe()
870 mutex_init(&adc_dev->lock); in mt6359_auxadc_probe()
874 indio_dev->name = adc_dev->chip_info->model_name; in mt6359_auxadc_probe()
875 indio_dev->info = &mt6359_auxadc_iio_info; in mt6359_auxadc_probe()
876 indio_dev->modes = INDIO_DIRECT_MODE; in mt6359_auxadc_probe()
877 indio_dev->channels = adc_dev->chip_info->channels; in mt6359_auxadc_probe()
878 indio_dev->num_channels = adc_dev->chip_info->num_channels; in mt6359_auxadc_probe()
888 { .compatible = "mediatek,mt6357-auxadc", .data = &mt6357_chip_info },
889 { .compatible = "mediatek,mt6358-auxadc", .data = &mt6358_chip_info },
890 { .compatible = "mediatek,mt6359-auxadc", .data = &mt6359_chip_info },
891 { .compatible = "mediatek,mt6363-auxadc", .data = &mt6363_chip_info },
892 { .compatible = "mediatek,mt6373-auxadc", .data = &mt6373_chip_info },
899 .name = "mt6359-auxadc",