Lines Matching +full:meson +full:- +full:gxbb +full:- +full:efuse
1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
96 (8 + (((_chan) - 2) * 3))
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
172 /* temperature sensor calibration information in eFuse */
380 for (i = 0; i < indio_dev->num_channels; i++) in find_channel_by_num()
381 if (indio_dev->channels[i].channel == num) in find_channel_by_num()
382 return &indio_dev->channels[i]; in find_channel_by_num()
391 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_get_fifo_count()
402 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
404 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); in meson_sar_adc_calib_val()
418 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, in meson_sar_adc_wait_busy_clear()
430 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_set_chan7_mux()
435 priv->chan7_mux_sel = sel; in meson_sar_adc_set_chan7_mux()
443 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_read_raw_sample()
446 if (!wait_for_completion_timeout(&priv->done, in meson_sar_adc_read_raw_sample()
448 return -ETIMEDOUT; in meson_sar_adc_read_raw_sample()
453 return -EINVAL; in meson_sar_adc_read_raw_sample()
456 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); in meson_sar_adc_read_raw_sample()
458 if (fifo_chan != chan->address) { in meson_sar_adc_read_raw_sample()
460 fifo_chan, chan->address); in meson_sar_adc_read_raw_sample()
461 return -EINVAL; in meson_sar_adc_read_raw_sample()
465 fifo_val &= GENMASK(priv->param->resolution - 1, 0); in meson_sar_adc_read_raw_sample()
477 int val, address = chan->address; in meson_sar_adc_set_averaging()
480 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
485 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
501 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
506 chan->address); in meson_sar_adc_enable_channel()
507 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
511 chan->address); in meson_sar_adc_enable_channel()
512 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
517 chan->address); in meson_sar_adc_enable_channel()
518 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
522 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { in meson_sar_adc_enable_channel()
523 if (chan->type == IIO_TEMP) in meson_sar_adc_enable_channel()
528 regmap_update_bits(priv->regmap, in meson_sar_adc_enable_channel()
531 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) { in meson_sar_adc_enable_channel()
534 if (chan->channel == NUM_CHAN_7) in meson_sar_adc_enable_channel()
537 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS]; in meson_sar_adc_enable_channel()
538 if (sel != priv->chan7_mux_sel) in meson_sar_adc_enable_channel()
547 reinit_completion(&priv->done); in meson_sar_adc_start_sample_engine()
549 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
552 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
555 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
563 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
566 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
572 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
581 mutex_lock(&priv->lock); in meson_sar_adc_lock()
583 if (priv->param->has_bl30_integration) { in meson_sar_adc_lock()
585 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_lock()
594 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, in meson_sar_adc_lock()
598 mutex_unlock(&priv->lock); in meson_sar_adc_lock()
610 if (priv->param->has_bl30_integration) in meson_sar_adc_unlock()
612 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_unlock()
615 mutex_unlock(&priv->lock); in meson_sar_adc_unlock()
627 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); in meson_sar_adc_clear_fifo()
638 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_get_sample()
641 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) in meson_sar_adc_get_sample()
642 return -ENOTSUPP; in meson_sar_adc_get_sample()
663 chan->address, ret); in meson_sar_adc_get_sample()
675 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_iio_info_read_raw()
689 if (chan->type == IIO_VOLTAGE) { in meson_sar_adc_iio_info_read_raw()
690 ret = regulator_get_voltage(priv->vref); in meson_sar_adc_iio_info_read_raw()
697 *val2 = priv->param->resolution; in meson_sar_adc_iio_info_read_raw()
699 } else if (chan->type == IIO_TEMP) { in meson_sar_adc_iio_info_read_raw()
701 *val = priv->param->temperature_multiplier; in meson_sar_adc_iio_info_read_raw()
702 *val2 = priv->param->temperature_divider; in meson_sar_adc_iio_info_read_raw()
709 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
713 *val = priv->calibbias; in meson_sar_adc_iio_info_read_raw()
717 *val = priv->calibscale / MILLION; in meson_sar_adc_iio_info_read_raw()
718 *val2 = priv->calibscale % MILLION; in meson_sar_adc_iio_info_read_raw()
723 priv->param->temperature_divider, in meson_sar_adc_iio_info_read_raw()
724 priv->param->temperature_multiplier); in meson_sar_adc_iio_info_read_raw()
725 *val -= priv->temperature_sensor_adc_val; in meson_sar_adc_iio_info_read_raw()
729 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
737 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_clk_init()
743 return -ENOMEM; in meson_sar_adc_clk_init()
747 clk_parents[0] = __clk_get_name(priv->clkin); in meson_sar_adc_clk_init()
751 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
752 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; in meson_sar_adc_clk_init()
753 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; in meson_sar_adc_clk_init()
754 priv->clk_div.hw.init = &init; in meson_sar_adc_clk_init()
755 priv->clk_div.flags = 0; in meson_sar_adc_clk_init()
757 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); in meson_sar_adc_clk_init()
758 if (WARN_ON(IS_ERR(priv->adc_div_clk))) in meson_sar_adc_clk_init()
759 return PTR_ERR(priv->adc_div_clk); in meson_sar_adc_clk_init()
763 return -ENOMEM; in meson_sar_adc_clk_init()
767 clk_parents[0] = __clk_get_name(priv->adc_div_clk); in meson_sar_adc_clk_init()
771 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
772 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); in meson_sar_adc_clk_init()
773 priv->clk_gate.hw.init = &init; in meson_sar_adc_clk_init()
775 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); in meson_sar_adc_clk_init()
776 if (WARN_ON(IS_ERR(priv->adc_clk))) in meson_sar_adc_clk_init()
777 return PTR_ERR(priv->adc_clk); in meson_sar_adc_clk_init()
786 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_temp_sensor_init()
797 * was passed via nvmem-cells. in meson_sar_adc_temp_sensor_init()
799 if (ret == -ENODEV) in meson_sar_adc_temp_sensor_init()
805 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); in meson_sar_adc_temp_sensor_init()
806 if (IS_ERR(priv->tsc_regmap)) in meson_sar_adc_temp_sensor_init()
807 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), in meson_sar_adc_temp_sensor_init()
808 "failed to get amlogic,hhi-sysctrl regmap\n"); in meson_sar_adc_temp_sensor_init()
816 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); in meson_sar_adc_temp_sensor_init()
819 trimming_bits = priv->param->temperature_trimming_bits; in meson_sar_adc_temp_sensor_init()
820 trimming_mask = BIT(trimming_bits) - 1; in meson_sar_adc_temp_sensor_init()
822 priv->temperature_sensor_calibrated = in meson_sar_adc_temp_sensor_init()
824 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; in meson_sar_adc_temp_sensor_init()
829 priv->temperature_sensor_adc_val = buf[2]; in meson_sar_adc_temp_sensor_init()
830 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; in meson_sar_adc_temp_sensor_init()
831 priv->temperature_sensor_adc_val >>= trimming_bits; in meson_sar_adc_temp_sensor_init()
841 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_init()
850 if (priv->param->has_bl30_integration) { in meson_sar_adc_init()
856 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); in meson_sar_adc_init()
867 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_init()
871 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); in meson_sar_adc_init()
873 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
875 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
879 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
883 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
889 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
893 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
903 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
907 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
911 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
914 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
917 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
920 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
934 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); in meson_sar_adc_init()
936 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_init()
937 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
939 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
947 priv->temperature_sensor_coefficient); in meson_sar_adc_init()
948 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
951 if (priv->param->temperature_trimming_bits == 5) { in meson_sar_adc_init()
952 if (priv->temperature_sensor_coefficient & BIT(4)) in meson_sar_adc_init()
961 regmap_update_bits(priv->tsc_regmap, in meson_sar_adc_init()
967 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
969 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
974 priv->param->disable_ring_counter); in meson_sar_adc_init()
975 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
979 if (priv->param->has_reg11) { in meson_sar_adc_init()
980 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc); in meson_sar_adc_init()
981 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
984 if (priv->param->has_vref_select) { in meson_sar_adc_init()
986 priv->param->vref_select); in meson_sar_adc_init()
987 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
992 priv->param->vref_volatge); in meson_sar_adc_init()
993 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
997 priv->param->cmv_select); in meson_sar_adc_init()
998 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
1002 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); in meson_sar_adc_init()
1006 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); in meson_sar_adc_init()
1016 const struct meson_sar_adc_param *param = priv->param; in meson_sar_adc_set_bandgap()
1019 if (param->bandgap_reg == MESON_SAR_ADC_REG11) in meson_sar_adc_set_bandgap()
1024 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, in meson_sar_adc_set_bandgap()
1031 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_hw_enable()
1041 ret = regulator_enable(priv->vref); in meson_sar_adc_hw_enable()
1048 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_hw_enable()
1053 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
1058 ret = clk_prepare_enable(priv->adc_clk); in meson_sar_adc_hw_enable()
1069 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
1072 regulator_disable(priv->vref); in meson_sar_adc_hw_enable()
1090 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret)); in meson_sar_adc_hw_disable()
1092 clk_disable_unprepare(priv->adc_clk); in meson_sar_adc_hw_disable()
1094 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_disable()
1099 regulator_disable(priv->vref); in meson_sar_adc_hw_disable()
1112 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_irq()
1119 complete(&priv->done); in meson_sar_adc_irq()
1130 nominal0 = (1 << priv->param->resolution) / 4; in meson_sar_adc_calib()
1131 nominal1 = (1 << priv->param->resolution) * 3 / 4; in meson_sar_adc_calib()
1152 ret = -EINVAL; in meson_sar_adc_calib()
1156 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, in meson_sar_adc_calib()
1157 value1 - value0); in meson_sar_adc_calib()
1158 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, in meson_sar_adc_calib()
1171 if (chan->type == IIO_TEMP) in read_label()
1172 return sprintf(label, "temp-sensor\n"); in read_label()
1173 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS) in read_label()
1175 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]); in read_label()
1176 if (chan->type == IIO_VOLTAGE) in read_label()
1177 return sprintf(label, "channel-%d\n", chan->channel); in read_label()
1260 .name = "meson-meson8-saradc",
1265 .name = "meson-meson8b-saradc",
1270 .name = "meson-meson8m2-saradc",
1275 .name = "meson-gxbb-saradc",
1280 .name = "meson-gxl-saradc",
1285 .name = "meson-gxm-saradc",
1290 .name = "meson-axg-saradc",
1295 .name = "meson-g12a-saradc",
1300 .compatible = "amlogic,meson8-saradc",
1303 .compatible = "amlogic,meson8b-saradc",
1306 .compatible = "amlogic,meson8m2-saradc",
1309 .compatible = "amlogic,meson-gxbb-saradc",
1312 .compatible = "amlogic,meson-gxl-saradc",
1315 .compatible = "amlogic,meson-gxm-saradc",
1318 .compatible = "amlogic,meson-axg-saradc",
1321 .compatible = "amlogic,meson-g12a-saradc",
1332 struct device *dev = &pdev->dev; in meson_sar_adc_probe()
1339 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); in meson_sar_adc_probe()
1342 init_completion(&priv->done); in meson_sar_adc_probe()
1346 return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); in meson_sar_adc_probe()
1348 priv->param = match_data->param; in meson_sar_adc_probe()
1350 indio_dev->name = match_data->name; in meson_sar_adc_probe()
1351 indio_dev->modes = INDIO_DIRECT_MODE; in meson_sar_adc_probe()
1352 indio_dev->info = &meson_sar_adc_iio_info; in meson_sar_adc_probe()
1358 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); in meson_sar_adc_probe()
1359 if (IS_ERR(priv->regmap)) in meson_sar_adc_probe()
1360 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n"); in meson_sar_adc_probe()
1362 irq = irq_of_parse_and_map(dev->of_node, 0); in meson_sar_adc_probe()
1364 return dev_err_probe(dev, -EINVAL, "failed to get irq\n"); in meson_sar_adc_probe()
1370 priv->clkin = devm_clk_get(dev, "clkin"); in meson_sar_adc_probe()
1371 if (IS_ERR(priv->clkin)) in meson_sar_adc_probe()
1372 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); in meson_sar_adc_probe()
1374 priv->core_clk = devm_clk_get_enabled(dev, "core"); in meson_sar_adc_probe()
1375 if (IS_ERR(priv->core_clk)) in meson_sar_adc_probe()
1376 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); in meson_sar_adc_probe()
1378 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); in meson_sar_adc_probe()
1379 if (IS_ERR(priv->adc_clk)) in meson_sar_adc_probe()
1380 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); in meson_sar_adc_probe()
1382 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); in meson_sar_adc_probe()
1383 if (IS_ERR(priv->adc_sel_clk)) in meson_sar_adc_probe()
1384 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); in meson_sar_adc_probe()
1386 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ in meson_sar_adc_probe()
1387 if (!priv->adc_clk) { in meson_sar_adc_probe()
1393 priv->vref = devm_regulator_get(dev, "vref"); in meson_sar_adc_probe()
1394 if (IS_ERR(priv->vref)) in meson_sar_adc_probe()
1395 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); in meson_sar_adc_probe()
1397 priv->calibscale = MILLION; in meson_sar_adc_probe()
1399 if (priv->param->temperature_trimming_bits) { in meson_sar_adc_probe()
1405 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_probe()
1406 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; in meson_sar_adc_probe()
1407 indio_dev->num_channels = in meson_sar_adc_probe()
1410 indio_dev->channels = meson_sar_adc_iio_channels; in meson_sar_adc_probe()
1411 indio_dev->num_channels = in meson_sar_adc_probe()
1419 mutex_init(&priv->lock); in meson_sar_adc_probe()
1461 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_suspend()
1472 ret = clk_prepare_enable(priv->core_clk); in meson_sar_adc_resume()
1488 .name = "meson-saradc",
1497 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");