1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
96 					(8 + (((_chan) - 2) * 3))
153  * and u-boot source served as reference). These only seem to be relevant on
384 	for (i = 0; i < indio_dev->num_channels; i++)  in find_channel_by_num()
385 		if (indio_dev->channels[i].channel == num)  in find_channel_by_num()
386 			return &indio_dev->channels[i];  in find_channel_by_num()
395 	regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);  in meson_sar_adc_get_fifo_count()
406 	tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;  in meson_sar_adc_calib_val()
408 	return clamp(tmp, 0, (1 << priv->param->resolution) - 1);  in meson_sar_adc_calib_val()
422 	return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,  in meson_sar_adc_wait_busy_clear()
434 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_set_chan7_mux()
439 	priv->chan7_mux_sel = sel;  in meson_sar_adc_set_chan7_mux()
447 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_read_raw_sample()
450 	if (!wait_for_completion_timeout(&priv->done,  in meson_sar_adc_read_raw_sample()
452 		return -ETIMEDOUT;  in meson_sar_adc_read_raw_sample()
457 		return -EINVAL;  in meson_sar_adc_read_raw_sample()
460 	regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);  in meson_sar_adc_read_raw_sample()
462 	if (fifo_chan != chan->address) {  in meson_sar_adc_read_raw_sample()
464 			fifo_chan, chan->address);  in meson_sar_adc_read_raw_sample()
465 		return -EINVAL;  in meson_sar_adc_read_raw_sample()
469 	fifo_val &= GENMASK(priv->param->resolution - 1, 0);  in meson_sar_adc_read_raw_sample()
481 	int val, address = chan->address;  in meson_sar_adc_set_averaging()
484 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,  in meson_sar_adc_set_averaging()
489 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,  in meson_sar_adc_set_averaging()
505 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,  in meson_sar_adc_enable_channel()
510 			    chan->address);  in meson_sar_adc_enable_channel()
511 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,  in meson_sar_adc_enable_channel()
515 			    chan->address);  in meson_sar_adc_enable_channel()
516 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,  in meson_sar_adc_enable_channel()
521 			    chan->address);  in meson_sar_adc_enable_channel()
522 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,  in meson_sar_adc_enable_channel()
526 	if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {  in meson_sar_adc_enable_channel()
527 		if (chan->type == IIO_TEMP)  in meson_sar_adc_enable_channel()
532 		regmap_update_bits(priv->regmap,  in meson_sar_adc_enable_channel()
535 	} else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) {  in meson_sar_adc_enable_channel()
538 		if (chan->channel == NUM_CHAN_7)  in meson_sar_adc_enable_channel()
541 			sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS];  in meson_sar_adc_enable_channel()
542 		if (sel != priv->chan7_mux_sel)  in meson_sar_adc_enable_channel()
551 	reinit_completion(&priv->done);  in meson_sar_adc_start_sample_engine()
553 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
556 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
559 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
567 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
570 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
576 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
585 	mutex_lock(&priv->lock);  in meson_sar_adc_lock()
587 	if (priv->param->has_bl30_integration) {  in meson_sar_adc_lock()
589 		regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_lock()
598 		ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,  in meson_sar_adc_lock()
602 			mutex_unlock(&priv->lock);  in meson_sar_adc_lock()
614 	if (priv->param->has_bl30_integration)  in meson_sar_adc_unlock()
616 		regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_unlock()
619 	mutex_unlock(&priv->lock);  in meson_sar_adc_unlock()
631 		regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);  in meson_sar_adc_clear_fifo()
642 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_get_sample()
645 	if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)  in meson_sar_adc_get_sample()
646 		return -ENOTSUPP;  in meson_sar_adc_get_sample()
667 			 chan->address, ret);  in meson_sar_adc_get_sample()
679 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_iio_info_read_raw()
693 		if (chan->type == IIO_VOLTAGE) {  in meson_sar_adc_iio_info_read_raw()
694 			ret = regulator_get_voltage(priv->vref);  in meson_sar_adc_iio_info_read_raw()
701 			*val2 = priv->param->resolution;  in meson_sar_adc_iio_info_read_raw()
703 		} else if (chan->type == IIO_TEMP) {  in meson_sar_adc_iio_info_read_raw()
705 			*val = priv->param->temperature_multiplier;  in meson_sar_adc_iio_info_read_raw()
706 			*val2 = priv->param->temperature_divider;  in meson_sar_adc_iio_info_read_raw()
713 			return -EINVAL;  in meson_sar_adc_iio_info_read_raw()
717 		*val = priv->calibbias;  in meson_sar_adc_iio_info_read_raw()
721 		*val = priv->calibscale / MILLION;  in meson_sar_adc_iio_info_read_raw()
722 		*val2 = priv->calibscale % MILLION;  in meson_sar_adc_iio_info_read_raw()
727 					 priv->param->temperature_divider,  in meson_sar_adc_iio_info_read_raw()
728 					 priv->param->temperature_multiplier);  in meson_sar_adc_iio_info_read_raw()
729 		*val -= priv->temperature_sensor_adc_val;  in meson_sar_adc_iio_info_read_raw()
733 		return -EINVAL;  in meson_sar_adc_iio_info_read_raw()
741 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_clk_init()
747 		return -ENOMEM;  in meson_sar_adc_clk_init()
751 	clk_parents[0] = __clk_get_name(priv->clkin);  in meson_sar_adc_clk_init()
755 	priv->clk_div.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
756 	priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;  in meson_sar_adc_clk_init()
757 	priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;  in meson_sar_adc_clk_init()
758 	priv->clk_div.hw.init = &init;  in meson_sar_adc_clk_init()
759 	priv->clk_div.flags = 0;  in meson_sar_adc_clk_init()
761 	priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);  in meson_sar_adc_clk_init()
762 	if (WARN_ON(IS_ERR(priv->adc_div_clk)))  in meson_sar_adc_clk_init()
763 		return PTR_ERR(priv->adc_div_clk);  in meson_sar_adc_clk_init()
767 		return -ENOMEM;  in meson_sar_adc_clk_init()
771 	clk_parents[0] = __clk_get_name(priv->adc_div_clk);  in meson_sar_adc_clk_init()
775 	priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
776 	priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);  in meson_sar_adc_clk_init()
777 	priv->clk_gate.hw.init = &init;  in meson_sar_adc_clk_init()
779 	priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);  in meson_sar_adc_clk_init()
780 	if (WARN_ON(IS_ERR(priv->adc_clk)))  in meson_sar_adc_clk_init()
781 		return PTR_ERR(priv->adc_clk);  in meson_sar_adc_clk_init()
790 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_temp_sensor_init()
801 		 * was passed via nvmem-cells.  in meson_sar_adc_temp_sensor_init()
803 		if (ret == -ENODEV)  in meson_sar_adc_temp_sensor_init()
809 	priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");  in meson_sar_adc_temp_sensor_init()
810 	if (IS_ERR(priv->tsc_regmap))  in meson_sar_adc_temp_sensor_init()
811 		return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),  in meson_sar_adc_temp_sensor_init()
812 				     "failed to get amlogic,hhi-sysctrl regmap\n");  in meson_sar_adc_temp_sensor_init()
820 		return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");  in meson_sar_adc_temp_sensor_init()
823 	trimming_bits = priv->param->temperature_trimming_bits;  in meson_sar_adc_temp_sensor_init()
824 	trimming_mask = BIT(trimming_bits) - 1;  in meson_sar_adc_temp_sensor_init()
826 	priv->temperature_sensor_calibrated =  in meson_sar_adc_temp_sensor_init()
828 	priv->temperature_sensor_coefficient = buf[2] & trimming_mask;  in meson_sar_adc_temp_sensor_init()
833 	priv->temperature_sensor_adc_val = buf[2];  in meson_sar_adc_temp_sensor_init()
834 	priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;  in meson_sar_adc_temp_sensor_init()
835 	priv->temperature_sensor_adc_val >>= trimming_bits;  in meson_sar_adc_temp_sensor_init()
845 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_init()
854 	if (priv->param->has_bl30_integration) {  in meson_sar_adc_init()
860 		regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);  in meson_sar_adc_init()
871 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_init()
875 	regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);  in meson_sar_adc_init()
877 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
879 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
883 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
887 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
893 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
897 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
907 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
911 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
915 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
918 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
921 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
924 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
938 	regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);  in meson_sar_adc_init()
940 	if (priv->temperature_sensor_calibrated) {  in meson_sar_adc_init()
941 		regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_init()
943 		regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_init()
951 				    priv->temperature_sensor_coefficient);  in meson_sar_adc_init()
952 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_init()
955 		if (priv->param->temperature_trimming_bits == 5) {  in meson_sar_adc_init()
956 			if (priv->temperature_sensor_coefficient & BIT(4))  in meson_sar_adc_init()
963 			 * of the TSC is located in the HHI register area.  in meson_sar_adc_init()
965 			regmap_update_bits(priv->tsc_regmap,  in meson_sar_adc_init()
971 		regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_init()
973 		regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_init()
978 			    priv->param->disable_ring_counter);  in meson_sar_adc_init()
979 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
983 	if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) {  in meson_sar_adc_init()
984 		regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);  in meson_sar_adc_init()
985 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,  in meson_sar_adc_init()
988 		if (priv->param->has_vref_select) {  in meson_sar_adc_init()
990 					    priv->param->vref_select);  in meson_sar_adc_init()
991 			regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,  in meson_sar_adc_init()
996 				    priv->param->vref_voltage);  in meson_sar_adc_init()
997 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,  in meson_sar_adc_init()
1001 				    priv->param->cmv_select);  in meson_sar_adc_init()
1002 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,  in meson_sar_adc_init()
1005 		if (priv->param->enable_mpll_clock_workaround) {  in meson_sar_adc_init()
1008 			regmap_write(priv->regmap, MESON_SAR_ADC_REG12,  in meson_sar_adc_init()
1015 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);  in meson_sar_adc_init()
1019 	ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);  in meson_sar_adc_init()
1030 	if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11)  in meson_sar_adc_set_bandgap()
1031 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,  in meson_sar_adc_set_bandgap()
1035 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_set_bandgap()
1043 	struct device *dev = indio_dev->dev.parent;  in meson_sar_adc_hw_enable()
1053 	ret = regulator_enable(priv->vref);  in meson_sar_adc_hw_enable()
1060 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_hw_enable()
1065 	regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
1070 	ret = clk_prepare_enable(priv->adc_clk);  in meson_sar_adc_hw_enable()
1081 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
1084 	regulator_disable(priv->vref);  in meson_sar_adc_hw_enable()
1102 		dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret));  in meson_sar_adc_hw_disable()
1104 	clk_disable_unprepare(priv->adc_clk);  in meson_sar_adc_hw_disable()
1106 	regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_disable()
1111 	regulator_disable(priv->vref);  in meson_sar_adc_hw_disable()
1124 	regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);  in meson_sar_adc_irq()
1131 	complete(&priv->done);  in meson_sar_adc_irq()
1142 	nominal0 = (1 << priv->param->resolution) / 4;  in meson_sar_adc_calib()
1143 	nominal1 = (1 << priv->param->resolution) * 3 / 4;  in meson_sar_adc_calib()
1164 		ret = -EINVAL;  in meson_sar_adc_calib()
1168 	priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,  in meson_sar_adc_calib()
1169 				   value1 - value0);  in meson_sar_adc_calib()
1170 	priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,  in meson_sar_adc_calib()
1183 	if (chan->type == IIO_TEMP)  in read_label()
1184 		return sysfs_emit(label, "temp-sensor\n");  in read_label()
1185 	if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS)  in read_label()
1187 			       chan7_mux_names[chan->channel - NUM_MUX_0_VSS]);  in read_label()
1188 	if (chan->type == IIO_VOLTAGE)  in read_label()
1189 		return sysfs_emit(label, "channel-%d\n", chan->channel);  in read_label()
1273 	.name = "meson-meson8-saradc",
1278 	.name = "meson-meson8b-saradc",
1283 	.name = "meson-meson8m2-saradc",
1288 	.name = "meson-gxbb-saradc",
1293 	.name = "meson-gxl-saradc",
1298 	.name = "meson-gxlx-saradc",
1303 	.name = "meson-gxm-saradc",
1308 	.name = "meson-axg-saradc",
1313 	.name = "meson-g12a-saradc",
1318 		.compatible = "amlogic,meson8-saradc",
1321 		.compatible = "amlogic,meson8b-saradc",
1324 		.compatible = "amlogic,meson8m2-saradc",
1327 		.compatible = "amlogic,meson-gxbb-saradc",
1330 		.compatible = "amlogic,meson-gxl-saradc",
1333 		.compatible = "amlogic,meson-gxlx-saradc",
1336 		.compatible = "amlogic,meson-gxm-saradc",
1339 		.compatible = "amlogic,meson-axg-saradc",
1342 		.compatible = "amlogic,meson-g12a-saradc",
1353 	struct device *dev = &pdev->dev;  in meson_sar_adc_probe()
1360 		return -ENOMEM;  in meson_sar_adc_probe()
1363 	init_completion(&priv->done);  in meson_sar_adc_probe()
1367 		return dev_err_probe(dev, -ENODEV, "failed to get match data\n");  in meson_sar_adc_probe()
1369 	priv->param = match_data->param;  in meson_sar_adc_probe()
1371 	indio_dev->name = match_data->name;  in meson_sar_adc_probe()
1372 	indio_dev->modes = INDIO_DIRECT_MODE;  in meson_sar_adc_probe()
1373 	indio_dev->info = &meson_sar_adc_iio_info;  in meson_sar_adc_probe()
1379 	priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);  in meson_sar_adc_probe()
1380 	if (IS_ERR(priv->regmap))  in meson_sar_adc_probe()
1381 		return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n");  in meson_sar_adc_probe()
1383 	irq = irq_of_parse_and_map(dev->of_node, 0);  in meson_sar_adc_probe()
1385 		return dev_err_probe(dev, -EINVAL, "failed to get irq\n");  in meson_sar_adc_probe()
1391 	priv->clkin = devm_clk_get(dev, "clkin");  in meson_sar_adc_probe()
1392 	if (IS_ERR(priv->clkin))  in meson_sar_adc_probe()
1393 		return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");  in meson_sar_adc_probe()
1395 	priv->core_clk = devm_clk_get_enabled(dev, "core");  in meson_sar_adc_probe()
1396 	if (IS_ERR(priv->core_clk))  in meson_sar_adc_probe()
1397 		return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");  in meson_sar_adc_probe()
1399 	priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");  in meson_sar_adc_probe()
1400 	if (IS_ERR(priv->adc_clk))  in meson_sar_adc_probe()
1401 		return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");  in meson_sar_adc_probe()
1403 	priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");  in meson_sar_adc_probe()
1404 	if (IS_ERR(priv->adc_sel_clk))  in meson_sar_adc_probe()
1405 		return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");  in meson_sar_adc_probe()
1407 	/* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */  in meson_sar_adc_probe()
1408 	if (!priv->adc_clk) {  in meson_sar_adc_probe()
1414 	priv->vref = devm_regulator_get(dev, "vref");  in meson_sar_adc_probe()
1415 	if (IS_ERR(priv->vref))  in meson_sar_adc_probe()
1416 		return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");  in meson_sar_adc_probe()
1418 	priv->calibscale = MILLION;  in meson_sar_adc_probe()
1420 	if (priv->param->temperature_trimming_bits) {  in meson_sar_adc_probe()
1426 	if (priv->temperature_sensor_calibrated) {  in meson_sar_adc_probe()
1427 		indio_dev->channels = meson_sar_adc_and_temp_iio_channels;  in meson_sar_adc_probe()
1428 		indio_dev->num_channels =  in meson_sar_adc_probe()
1431 		indio_dev->channels = meson_sar_adc_iio_channels;  in meson_sar_adc_probe()
1432 		indio_dev->num_channels =  in meson_sar_adc_probe()
1440 	mutex_init(&priv->lock);  in meson_sar_adc_probe()
1482 	clk_disable_unprepare(priv->core_clk);  in meson_sar_adc_suspend()
1493 	ret = clk_prepare_enable(priv->core_clk);  in meson_sar_adc_resume()
1509 		.name	= "meson-saradc",