Lines Matching +full:adc +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
85 /* Maximal number of channels used by the MCP39XX family */
103 const struct iio_chan_spec *channels; member
106 int (*config)(struct mcp3911 *adc, bool external_vref);
107 int (*get_osr)(struct mcp3911 *adc, u32 *val);
108 int (*set_osr)(struct mcp3911 *adc, u32 val);
109 int (*enable_offset)(struct mcp3911 *adc, bool enable);
110 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
111 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
112 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
124 u32 channels[MCP39XX_MAX_NUM_CHANNELS]; member
132 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) in mcp3911_read() argument
136 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
137 ret = spi_write_then_read(adc->spi, ®, 1, val, len); in mcp3911_read()
142 *val >>= ((4 - len) * 8); in mcp3911_read()
143 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, in mcp3911_read()
148 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) in mcp3911_write() argument
150 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); in mcp3911_write()
152 val <<= (3 - len) * 8; in mcp3911_write()
154 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); in mcp3911_write()
156 return spi_write(adc->spi, &val, len + 1); in mcp3911_write()
159 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) in mcp3911_update() argument
164 ret = mcp3911_read(adc, reg, &tmp, len); in mcp3911_update()
170 return mcp3911_write(adc, reg, val, len); in mcp3911_update()
173 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) in mcp3910_enable_offset() argument
178 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); in mcp3910_enable_offset()
181 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) in mcp3910_get_offset() argument
183 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); in mcp3910_get_offset()
186 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) in mcp3910_set_offset() argument
190 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); in mcp3910_set_offset()
194 return adc->chip->enable_offset(adc, 1); in mcp3910_set_offset()
197 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) in mcp3911_enable_offset() argument
202 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); in mcp3911_enable_offset()
205 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) in mcp3911_get_offset() argument
207 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); in mcp3911_get_offset()
210 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) in mcp3911_set_offset() argument
214 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); in mcp3911_set_offset()
218 return adc->chip->enable_offset(adc, 1); in mcp3911_set_offset()
221 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) in mcp3910_get_osr() argument
226 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); in mcp3910_get_osr()
235 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) in mcp3910_set_osr() argument
240 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); in mcp3910_set_osr()
243 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) in mcp3911_set_osr() argument
248 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); in mcp3911_set_osr()
251 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) in mcp3911_get_osr() argument
256 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); in mcp3911_get_osr()
265 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) in mcp3910_set_scale() argument
267 return mcp3911_update(adc, MCP3910_REG_GAIN, in mcp3910_set_scale()
272 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) in mcp3911_set_scale() argument
274 return mcp3911_update(adc, MCP3911_REG_GAIN, in mcp3911_set_scale()
310 return -EINVAL; in mcp3911_read_avail()
318 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_read_raw() local
321 guard(mutex)(&adc->lock); in mcp3911_read_raw()
324 ret = mcp3911_read(adc, in mcp3911_read_raw()
325 MCP3911_CHANNEL(channel->channel), val, 3); in mcp3911_read_raw()
332 ret = adc->chip->get_offset(adc, channel->channel, val); in mcp3911_read_raw()
338 ret = adc->chip->get_osr(adc, val); in mcp3911_read_raw()
344 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0]; in mcp3911_read_raw()
345 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1]; in mcp3911_read_raw()
348 return -EINVAL; in mcp3911_read_raw()
356 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_write_raw() local
358 guard(mutex)(&adc->lock); in mcp3911_write_raw()
365 adc->gain[channel->channel] = BIT(i); in mcp3911_write_raw()
366 return adc->chip->set_scale(adc, channel->channel, i); in mcp3911_write_raw()
369 return -EINVAL; in mcp3911_write_raw()
372 return -EINVAL; in mcp3911_write_raw()
374 return adc->chip->set_offset(adc, channel->channel, val); in mcp3911_write_raw()
378 return adc->chip->set_osr(adc, i); in mcp3911_write_raw()
381 return -EINVAL; in mcp3911_write_raw()
383 return -EINVAL; in mcp3911_write_raw()
393 * For 24-bit Conversion in mcp3911_calc_scale_table()
489 struct iio_dev *indio_dev = pf->indio_dev; in mcp3911_trigger_handler()
490 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_trigger_handler() local
491 struct device *dev = &adc->spi->dev; in mcp3911_trigger_handler()
494 .tx_buf = &adc->tx_buf, in mcp3911_trigger_handler()
497 .rx_buf = adc->rx_buf, in mcp3911_trigger_handler()
498 .len = (adc->chip->num_channels - 1) * 3, in mcp3911_trigger_handler()
505 guard(mutex)(&adc->lock); in mcp3911_trigger_handler()
506 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); in mcp3911_trigger_handler()
507 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); in mcp3911_trigger_handler()
514 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index]; in mcp3911_trigger_handler()
516 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]); in mcp3911_trigger_handler()
519 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan, in mcp3911_trigger_handler()
522 iio_trigger_notify_done(indio_dev->trig); in mcp3911_trigger_handler()
534 static int mcp3911_config(struct mcp3911 *adc, bool external_vref) in mcp3911_config() argument
536 struct device *dev = &adc->spi->dev; in mcp3911_config()
540 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2); in mcp3911_config()
554 if (adc->clki) { in mcp3911_config()
562 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); in mcp3911_config()
566 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2); in mcp3911_config()
575 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) in mcp3911_config()
583 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); in mcp3911_config()
587 /* Set gain to 1 for all channels */ in mcp3911_config()
588 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1); in mcp3911_config()
592 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3911_config()
593 adc->gain[i] = 1; in mcp3911_config()
597 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); in mcp3911_config()
600 static int mcp3910_config(struct mcp3911 *adc, bool external_vref) in mcp3910_config() argument
602 struct device *dev = &adc->spi->dev; in mcp3910_config()
606 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3); in mcp3910_config()
620 if (adc->clki) { in mcp3910_config()
628 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); in mcp3910_config()
632 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3); in mcp3910_config()
641 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) in mcp3910_config()
646 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); in mcp3910_config()
650 /* Set gain to 1 for all channels */ in mcp3910_config()
651 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3); in mcp3910_config()
655 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3910_config()
656 adc->gain[i] = 1; in mcp3910_config()
659 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); in mcp3910_config()
664 return adc->chip->enable_offset(adc, 0); in mcp3910_config()
669 struct mcp3911 *adc = iio_trigger_get_drvdata(trig); in mcp3911_set_trigger_state() local
672 enable_irq(adc->spi->irq); in mcp3911_set_trigger_state()
674 disable_irq(adc->spi->irq); in mcp3911_set_trigger_state()
686 struct device *dev = &spi->dev; in mcp3911_probe()
688 struct mcp3911 *adc; in mcp3911_probe() local
693 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); in mcp3911_probe()
695 return -ENOMEM; in mcp3911_probe()
697 adc = iio_priv(indio_dev); in mcp3911_probe()
698 adc->spi = spi; in mcp3911_probe()
699 adc->chip = spi_get_device_match_data(spi); in mcp3911_probe()
702 if (ret < 0 && ret != -ENODEV) in mcp3911_probe()
705 external_vref = ret != -ENODEV; in mcp3911_probe()
708 adc->clki = devm_clk_get_enabled(dev, NULL); in mcp3911_probe()
709 if (IS_ERR(adc->clki)) { in mcp3911_probe()
710 if (PTR_ERR(adc->clki) == -ENOENT) { in mcp3911_probe()
711 adc->clki = NULL; in mcp3911_probe()
713 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n"); in mcp3911_probe()
718 * Fallback to "device-addr" due to historical mismatch between in mcp3911_probe()
719 * dt-bindings and implementation. in mcp3911_probe()
721 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); in mcp3911_probe()
723 device_property_read_u32(dev, "device-addr", &adc->dev_addr); in mcp3911_probe()
724 if (adc->dev_addr > 3) { in mcp3911_probe()
725 return dev_err_probe(dev, -EINVAL, in mcp3911_probe()
726 "invalid device address (%i). Must be in range 0-3.\n", in mcp3911_probe()
727 adc->dev_addr); in mcp3911_probe()
729 dev_dbg(dev, "use device address %i\n", adc->dev_addr); in mcp3911_probe()
731 ret = adc->chip->config(adc, external_vref); in mcp3911_probe()
739 /* Set gain to 1 for all channels */ in mcp3911_probe()
740 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3911_probe()
741 adc->gain[i] = 1; in mcp3911_probe()
742 ret = mcp3911_update(adc, MCP3911_REG_GAIN, in mcp3911_probe()
749 indio_dev->name = spi_get_device_id(spi)->name; in mcp3911_probe()
750 indio_dev->modes = INDIO_DIRECT_MODE; in mcp3911_probe()
751 indio_dev->info = &mcp3911_info; in mcp3911_probe()
754 indio_dev->channels = adc->chip->channels; in mcp3911_probe()
755 indio_dev->num_channels = adc->chip->num_channels; in mcp3911_probe()
757 mutex_init(&adc->lock); in mcp3911_probe()
759 if (spi->irq > 0) { in mcp3911_probe()
760 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, in mcp3911_probe()
762 if (!adc->trig) in mcp3911_probe()
763 return -ENOMEM; in mcp3911_probe()
765 adc->trig->ops = &mcp3911_trigger_ops; in mcp3911_probe()
766 iio_trigger_set_drvdata(adc->trig, adc); in mcp3911_probe()
767 ret = devm_iio_trigger_register(dev, adc->trig); in mcp3911_probe()
776 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll, in mcp3911_probe()
778 indio_dev->name, adc->trig); in mcp3911_probe()
793 .channels = mcp3910_channels,
804 .channels = mcp3911_channels,
815 .channels = mcp3912_channels,
826 .channels = mcp3913_channels,
837 .channels = mcp3914_channels,
848 .channels = mcp3918_channels,
859 .channels = mcp3919_channels,