Lines Matching +full:diff +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-only
142 struct max11410_channel_config *channels;
175 /* This driver only needs to write 8-bit registers */
177 return -EINVAL;
179 return regmap_write(st->regmap, reg, val);
188 ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3);
192 *val = get_unaligned_be24(&st->scan.data);
196 return regmap_read(st->regmap, reg, val);
204 return st->avdd;
206 return st->vrefp[refsel];
215 return st->vrefn[refsel];
238 switch (iio_attr->address) {
249 return -EINVAL;
270 switch (iio_attr->address) {
285 ret = regmap_clear_bits(state->regmap, MAX11410_REG_FILTER,
288 ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER,
305 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®);
311 max11410_sampling_len[MAX11410_FILTER_SINC4] - 1);
346 return -EINVAL;
355 struct max11410_channel_config cfg = st->channels[chan->address];
359 if (chan->differential)
360 ret = max11410_set_input_mux(st, chan->channel, chan->channel2);
362 ret = max11410_set_input_mux(st, chan->channel,
372 ret = regmap_update_bits(st->regmap, MAX11410_REG_CTRL,
382 ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval);
401 if (st->irq > 0)
402 reinit_completion(&st->completion);
410 if (st->irq > 0) {
412 ret = wait_for_completion_timeout(&st->completion,
415 return -ETIMEDOUT;
445 scale -= regulator_get_voltage(vrefn) / 1000;
458 struct max11410_channel_config cfg = state->channels[chan->address];
464 *val2 = chan->scan_type.realbits;
468 *val = -BIT(chan->scan_type.realbits - 1);
478 mutex_lock(&state->lock);
482 mutex_unlock(&state->lock);
493 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®_val);
500 rate = max11410_sampling_len[filter] - 1;
507 return -EINVAL;
520 scale_avail = st->channels[chan->address].scale_avail;
522 return -EOPNOTSUPP;
526 return -EINVAL;
537 st->channels[chan->address].gain = clamp_val(gain, 0, 7);
547 mutex_lock(&st->lock);
549 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
561 ret = -EINVAL;
565 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
569 mutex_unlock(&st->lock);
574 return -EINVAL;
589 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
601 cfg = st->channels[chan->address];
604 return -EINVAL;
612 return -EINVAL;
625 struct iio_dev *indio_dev = pf->indio_dev;
629 ret = max11410_read_reg(st, MAX11410_REG_DATA0, &st->scan.data);
631 dev_err(&indio_dev->dev, "cannot read data\n");
635 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan,
639 iio_trigger_notify_done(indio_dev->trig);
649 scan_ch = ffs(*indio_dev->active_scan_mask) - 1;
651 ret = max11410_configure_channel(st, &indio_dev->channels[scan_ch]);
685 iio_trigger_poll_nested(st->trig);
687 complete(&st->completion);
696 struct device *dev = &st->spi_dev->dev;
698 struct iio_chan_spec *channels;
708 return dev_err_probe(&indio_dev->dev, -ENODEV,
709 "FW has no channels defined\n");
713 channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL);
714 if (!channels)
715 return -ENOMEM;
717 st->channels = devm_kcalloc(dev, num_ch, sizeof(*st->channels),
719 if (!st->channels)
720 return -ENOMEM;
724 if (fwnode_property_present(child, "diff-channels")) {
726 "diff-channels",
742 return dev_err_probe(&indio_dev->dev, -EINVAL,
747 cfg = &st->channels[chan_idx];
752 return dev_err_probe(&indio_dev->dev, -EINVAL,
758 return dev_err_probe(&indio_dev->dev, -EINVAL,
763 fwnode_property_read_u32(child, "adi,input-mode", &sig_path);
765 return dev_err_probe(&indio_dev->dev, -EINVAL,
766 "Invalid adi,input-mode value for %s, should be less than %d.\n",
769 fwnode_property_read_u32(child, "settling-time-us",
770 &cfg->settling_time_us);
771 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
772 cfg->buffered_vrefp = fwnode_property_read_bool(child, "adi,buffered-vrefp");
773 cfg->buffered_vrefn = fwnode_property_read_bool(child, "adi,buffered-vrefn");
774 cfg->refsel = reference;
775 cfg->sig_path = sig_path;
776 cfg->gain = 0;
782 cfg->scale_avail = devm_kcalloc(dev, MAX11410_SCALE_AVAIL_SIZE * 2,
783 sizeof(*cfg->scale_avail),
785 if (!cfg->scale_avail)
786 return -ENOMEM;
790 cfg->scale_avail[2 * i] = scale >> i;
791 cfg->scale_avail[2 * i + 1] = chanspec.scan_type.realbits;
803 channels[chan_idx] = chanspec;
807 channels[chan_idx] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(chan_idx);
809 indio_dev->num_channels = chan_idx + 1;
810 indio_dev->channels = channels;
828 if (PTR_ERR(reg) == -ENODEV) {
866 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
877 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
886 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
897 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
902 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
907 return regmap_write_bits(st->regmap, MAX11410_REG_PGA,
917 struct device *dev = &spi->dev;
925 return -ENOMEM;
928 st->spi_dev = spi;
929 init_completion(&st->completion);
930 mutex_init(&st->lock);
932 indio_dev->name = "max11410";
933 indio_dev->modes = INDIO_DIRECT_MODE;
934 indio_dev->info = &max11410_info;
936 st->regmap = devm_regmap_init_spi(spi, ®map_config);
937 if (IS_ERR(st->regmap))
938 return dev_err_probe(dev, PTR_ERR(st->regmap),
941 ret = max11410_init_vref(dev, &st->avdd, "avdd");
946 ret = max11410_init_vref(dev, &st->vrefp[i], vrefp_regs[i]);
950 ret = max11410_init_vref(dev, &st->vrefn[i], vrefn_regs[i]);
956 * Regulators must be configured before parsing channels for
967 st->irq = irqs[0];
968 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(0),
971 st->irq = irqs[1];
972 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(1),
974 } else if (spi->irq > 0) {
975 return dev_err_probe(dev, -ENODEV,
982 ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL,
993 if (st->irq > 0) {
994 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
995 indio_dev->name,
997 if (!st->trig)
998 return -ENOMEM;
1000 st->trig->ops = &max11410_trigger_ops;
1001 ret = devm_iio_trigger_register(dev, st->trig);
1005 ret = devm_request_threaded_irq(dev, st->irq, NULL,