Lines Matching +full:dsp +full:- +full:clkout
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
132 * 3P4W Wye = 3-Phase 4-Wire star configuration (3 phases + neutral wire)
135 * 3Wire delta = 3-Phase 3-Wire triangle configuration (3 phases, no neutral)
159 /* DSP ON */
289 * Calculate register address for multi-phase device.
343 /* Zero crossing detection - datasheet: ZXV interrupts */
353 /* Zero crossing detection - datasheet: ZXI interrupts */
390 ret = regmap_read(st->regmap, ADE9000_REG_WFB_CFG, &val); in ade9000_filter_type_get()
401 return -EINVAL; in ade9000_filter_type_get()
412 return -EINVAL; in ade9000_filter_type_set()
417 ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG, in ade9000_filter_type_set()
424 st->wf_src = val; in ade9000_filter_type_set()
492 .scan_index = -1 \
507 .scan_index = -1 \
521 .scan_index = -1 \
534 .scan_index = -1 \
546 .scan_index = -1 \
557 .scan_index = -1 \
568 .scan_index = -1 \
579 .scan_index = -1 \
588 .scan_index = -1 \
660 guard(mutex)(&st->lock); in ade9000_spi_write_reg()
673 ret = spi_write_then_read(st->spi, tx_buf, len, NULL, 0); in ade9000_spi_write_reg()
675 dev_err(&st->spi->dev, "problem when writing register 0x%x\n", reg); in ade9000_spi_write_reg()
689 guard(mutex)(&st->lock); in ade9000_spi_read_reg()
696 /* Skip CRC bytes - only read actual data */ in ade9000_spi_read_reg()
702 ret = spi_write_then_read(st->spi, tx_buf, 2, rx_buf, rx_len); in ade9000_spi_read_reg()
704 dev_err(&st->spi->dev, "error reading register 0x%x\n", reg); in ade9000_spi_read_reg()
719 /* Interrupt/error status registers - volatile */ in ade9000_is_volatile_reg()
724 /* All other registers are non-volatile */ in ade9000_is_volatile_reg()
737 put_unaligned_be16(addr, st->tx_buff); in ade9000_configure_scan()
739 st->xfer[0].tx_buf = &st->tx_buff[0]; in ade9000_configure_scan()
740 st->xfer[0].len = 2; in ade9000_configure_scan()
742 st->xfer[1].rx_buf = st->rx_buff.byte; in ade9000_configure_scan()
745 st->xfer[1].len = (st->wfb_nr_samples / 2) * 4; in ade9000_configure_scan()
747 spi_message_init_with_transfers(&st->spi_msg, st->xfer, ARRAY_SIZE(st->xfer)); in ade9000_configure_scan()
753 struct device *dev = &st->spi->dev; in ade9000_iio_push_streaming()
757 guard(mutex)(&st->lock); in ade9000_iio_push_streaming()
759 ret = spi_sync(st->spi, &st->spi_msg); in ade9000_iio_push_streaming()
766 for (i = 0; i < st->wfb_nr_samples / 2; i += st->wfb_nr_activ_chan) in ade9000_iio_push_streaming()
767 iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]); in ade9000_iio_push_streaming()
769 ret = regmap_read(st->regmap, ADE9000_REG_WFB_PG_IRQEN, ¤t_page); in ade9000_iio_push_streaming()
776 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN, in ade9000_iio_push_streaming()
786 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN, in ade9000_iio_push_streaming()
805 guard(mutex)(&st->lock); in ade9000_iio_push_buffer()
807 ret = spi_sync(st->spi, &st->spi_msg); in ade9000_iio_push_buffer()
809 dev_err_ratelimited(&st->spi->dev, in ade9000_iio_push_buffer()
814 for (i = 0; i < st->wfb_nr_samples; i += st->wfb_nr_activ_chan) in ade9000_iio_push_buffer()
815 iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]); in ade9000_iio_push_buffer()
824 struct device *dev = &st->spi->dev; in ade9000_irq0_thread()
829 ret = regmap_read(st->regmap, ADE9000_REG_STATUS0, &status); in ade9000_irq0_thread()
835 ret = regmap_read(st->regmap, ADE9000_REG_MASK0, &interrupts); in ade9000_irq0_thread()
855 ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG, in ade9000_irq0_thread()
874 ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, handled_irq); in ade9000_irq0_thread()
893 if (!completion_done(&st->reset_completion)) { in ade9000_irq1_thread()
894 ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &result); in ade9000_irq1_thread()
896 dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n"); in ade9000_irq1_thread()
901 complete(&st->reset_completion); in ade9000_irq1_thread()
903 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, ADE9000_ST1_RSTDONE_BIT); in ade9000_irq1_thread()
905 dev_err_ratelimited(&st->spi->dev, in ade9000_irq1_thread()
908 dev_err_ratelimited(&st->spi->dev, in ade9000_irq1_thread()
915 ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &status); in ade9000_irq1_thread()
917 dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n"); in ade9000_irq1_thread()
921 ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts); in ade9000_irq1_thread()
923 dev_err_ratelimited(&st->spi->dev, "IRQ1 read mask fail\n"); in ade9000_irq1_thread()
946 IIO_UNMOD_EVENT_CODE(event->chan_type, in ade9000_irq1_thread()
947 event->channel, in ade9000_irq1_thread()
948 event->event_type, in ade9000_irq1_thread()
949 event->event_dir), in ade9000_irq1_thread()
955 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, handled_irq); in ade9000_irq1_thread()
957 dev_err_ratelimited(&st->spi->dev, "IRQ1 write status fail\n"); in ade9000_irq1_thread()
987 if (chan->type == IIO_VOLTAGE) { in ade9000_read_raw()
991 switch (chan->channel) { in ade9000_read_raw()
1002 return -EINVAL; in ade9000_read_raw()
1004 ret = regmap_read(st->regmap, period_reg, &period); in ade9000_read_raw()
1017 return -EINVAL; in ade9000_read_raw()
1019 if (chan->type == IIO_ENERGY) { in ade9000_read_raw()
1020 u16 lo_reg = chan->address; in ade9000_read_raw()
1022 ret = regmap_bulk_read(st->regmap, lo_reg, in ade9000_read_raw()
1023 st->bulk_read_buf, 2); in ade9000_read_raw()
1027 *val = st->bulk_read_buf[0]; /* Lower 32 bits */ in ade9000_read_raw()
1028 *val2 = st->bulk_read_buf[1]; /* Upper 32 bits */ in ade9000_read_raw()
1033 return -EBUSY; in ade9000_read_raw()
1035 ret = regmap_read(st->regmap, chan->address, &measured); in ade9000_read_raw()
1046 return -EBUSY; in ade9000_read_raw()
1048 ret = regmap_read(st->regmap, chan->address, &measured); in ade9000_read_raw()
1058 switch (chan->type) { in ade9000_read_raw()
1063 switch (chan->address) { in ade9000_read_raw()
1083 return -EINVAL; in ade9000_read_raw()
1093 return -EINVAL; in ade9000_read_raw()
1095 return -EINVAL; in ade9000_read_raw()
1110 switch (chan->type) { in ade9000_write_raw()
1112 return regmap_write(st->regmap, in ade9000_write_raw()
1114 chan->channel), val); in ade9000_write_raw()
1117 return regmap_write(st->regmap, in ade9000_write_raw()
1119 chan->channel), val); in ade9000_write_raw()
1121 tmp = chan->address; in ade9000_write_raw()
1127 return regmap_write(st->regmap, in ade9000_write_raw()
1129 chan->channel), val); in ade9000_write_raw()
1131 return regmap_write(st->regmap, in ade9000_write_raw()
1133 chan->channel), val); in ade9000_write_raw()
1135 return regmap_write(st->regmap, in ade9000_write_raw()
1137 chan->channel), val); in ade9000_write_raw()
1139 return -EINVAL; in ade9000_write_raw()
1142 return -EINVAL; in ade9000_write_raw()
1146 * Calibration gain registers for fine-tuning measurements. in ade9000_write_raw()
1149 switch (chan->type) { in ade9000_write_raw()
1151 return regmap_write(st->regmap, in ade9000_write_raw()
1153 chan->channel), val); in ade9000_write_raw()
1155 return regmap_write(st->regmap, in ade9000_write_raw()
1157 chan->channel), val); in ade9000_write_raw()
1159 return regmap_write(st->regmap, in ade9000_write_raw()
1161 chan->channel), val); in ade9000_write_raw()
1163 return -EINVAL; in ade9000_write_raw()
1166 /* Per-channel scales are read-only */ in ade9000_write_raw()
1167 return -EINVAL; in ade9000_write_raw()
1169 return -EINVAL; in ade9000_write_raw()
1181 return regmap_read(st->regmap, reg, rx_val); in ade9000_reg_access()
1183 return regmap_write(st->regmap, reg, tx_val); in ade9000_reg_access()
1196 ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts1); in ade9000_read_event_config()
1200 switch (chan->channel) { in ade9000_read_event_config()
1202 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1204 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1206 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) in ade9000_read_event_config()
1208 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) in ade9000_read_event_config()
1210 dev_err_ratelimited(&indio_dev->dev, in ade9000_read_event_config()
1211 "Invalid channel type %d or direction %d for phase A\n", chan->type, dir); in ade9000_read_event_config()
1212 return -EINVAL; in ade9000_read_event_config()
1214 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1216 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1218 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) in ade9000_read_event_config()
1220 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) in ade9000_read_event_config()
1222 dev_err_ratelimited(&indio_dev->dev, in ade9000_read_event_config()
1223 "Invalid channel type %d or direction %d for phase B\n", chan->type, dir); in ade9000_read_event_config()
1224 return -EINVAL; in ade9000_read_event_config()
1226 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1228 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) in ade9000_read_event_config()
1230 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) in ade9000_read_event_config()
1232 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) in ade9000_read_event_config()
1234 dev_err_ratelimited(&indio_dev->dev, in ade9000_read_event_config()
1235 "Invalid channel type %d or direction %d for phase C\n", chan->type, dir); in ade9000_read_event_config()
1236 return -EINVAL; in ade9000_read_event_config()
1238 return -EINVAL; in ade9000_read_event_config()
1253 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, GENMASK(31, 0)); in ade9000_write_event_config()
1258 switch (chan->channel) { in ade9000_write_event_config()
1260 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1263 st->wfb_trg |= ADE9000_WFB_TRG_ZXVA_BIT; in ade9000_write_event_config()
1265 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVA_BIT; in ade9000_write_event_config()
1266 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1269 st->wfb_trg |= ADE9000_WFB_TRG_ZXIA_BIT; in ade9000_write_event_config()
1271 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIA_BIT; in ade9000_write_event_config()
1272 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) { in ade9000_write_event_config()
1275 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1277 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1278 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) { in ade9000_write_event_config()
1281 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1283 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1285 dev_err_ratelimited(&indio_dev->dev, "Invalid channel type %d or direction %d for phase A\n", in ade9000_write_event_config()
1286 chan->type, dir); in ade9000_write_event_config()
1287 return -EINVAL; in ade9000_write_event_config()
1291 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1294 st->wfb_trg |= ADE9000_WFB_TRG_ZXVB_BIT; in ade9000_write_event_config()
1296 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVB_BIT; in ade9000_write_event_config()
1297 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1300 st->wfb_trg |= ADE9000_WFB_TRG_ZXIB_BIT; in ade9000_write_event_config()
1302 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIB_BIT; in ade9000_write_event_config()
1303 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) { in ade9000_write_event_config()
1306 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1308 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1309 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) { in ade9000_write_event_config()
1312 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1314 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1316 dev_err_ratelimited(&indio_dev->dev, in ade9000_write_event_config()
1318 chan->type, dir); in ade9000_write_event_config()
1319 return -EINVAL; in ade9000_write_event_config()
1323 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1326 st->wfb_trg |= ADE9000_WFB_TRG_ZXVC_BIT; in ade9000_write_event_config()
1328 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVC_BIT; in ade9000_write_event_config()
1329 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) { in ade9000_write_event_config()
1332 st->wfb_trg |= ADE9000_WFB_TRG_ZXIC_BIT; in ade9000_write_event_config()
1334 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIC_BIT; in ade9000_write_event_config()
1335 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) { in ade9000_write_event_config()
1338 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1340 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT; in ade9000_write_event_config()
1341 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) { in ade9000_write_event_config()
1344 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1346 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT; in ade9000_write_event_config()
1348 dev_err_ratelimited(&indio_dev->dev, in ade9000_write_event_config()
1350 chan->type, dir); in ade9000_write_event_config()
1351 return -EINVAL; in ade9000_write_event_config()
1355 return -EINVAL; in ade9000_write_event_config()
1359 return regmap_assign_bits(st->regmap, ADE9000_REG_MASK1, bit_mask, state ? bit_mask : 0); in ade9000_write_event_config()
1375 return regmap_write(st->regmap, ADE9000_REG_DIP_LVL, val); in ade9000_write_event_value()
1377 return regmap_write(st->regmap, ADE9000_REG_SWELL_LVL, val); in ade9000_write_event_value()
1379 return -EINVAL; in ade9000_write_event_value()
1382 return -EINVAL; in ade9000_write_event_value()
1401 ret = regmap_read(st->regmap, ADE9000_REG_DIP_LVL, &data); in ade9000_read_event_value()
1407 ret = regmap_read(st->regmap, ADE9000_REG_SWELL_LVL, &data); in ade9000_read_event_value()
1413 return -EINVAL; in ade9000_read_event_value()
1416 return -EINVAL; in ade9000_read_event_value()
1426 bitmap_to_arr32(&active_scans, indio_dev->active_scan_mask, in ade9000_waveform_buffer_config()
1432 st->wfb_nr_activ_chan = 2; in ade9000_waveform_buffer_config()
1436 st->wfb_nr_activ_chan = 2; in ade9000_waveform_buffer_config()
1440 st->wfb_nr_activ_chan = 2; in ade9000_waveform_buffer_config()
1444 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1448 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1452 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1456 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1460 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1464 st->wfb_nr_activ_chan = 1; in ade9000_waveform_buffer_config()
1469 st->wfb_nr_activ_chan = 6; in ade9000_waveform_buffer_config()
1472 dev_err(&st->spi->dev, "Unsupported combination of scans\n"); in ade9000_waveform_buffer_config()
1473 return -EINVAL; in ade9000_waveform_buffer_config()
1476 wfb_cfg_val |= FIELD_PREP(ADE9000_WF_SRC_MASK, st->wf_src); in ade9000_waveform_buffer_config()
1478 return regmap_write(st->regmap, ADE9000_REG_WFB_CFG, wfb_cfg_val); in ade9000_waveform_buffer_config()
1485 ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0); in ade9000_waveform_buffer_interrupt_setup()
1490 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN, in ade9000_waveform_buffer_interrupt_setup()
1495 ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0)); in ade9000_waveform_buffer_interrupt_setup()
1499 return regmap_set_bits(st->regmap, ADE9000_REG_MASK0, in ade9000_waveform_buffer_interrupt_setup()
1512 st->wfb_nr_samples = ADE9000_WFB_MAX_SAMPLES_CHAN * st->wfb_nr_activ_chan; in ade9000_buffer_preenable()
1520 ret = regmap_set_bits(st->regmap, ADE9000_REG_WFB_CFG, in ade9000_buffer_preenable()
1523 dev_err(&st->spi->dev, "Post-enable waveform buffer enable fail\n"); in ade9000_buffer_preenable()
1533 struct device *dev = &st->spi->dev; in ade9000_buffer_postdisable()
1537 ret = regmap_clear_bits(st->regmap, ADE9000_REG_WFB_CFG, in ade9000_buffer_postdisable()
1540 dev_err(dev, "Post-disable waveform buffer disable fail\n"); in ade9000_buffer_postdisable()
1544 ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0); in ade9000_buffer_postdisable()
1550 ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts); in ade9000_buffer_postdisable()
1552 dev_err(dev, "Post-disable update maks0 fail\n"); in ade9000_buffer_postdisable()
1556 return regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0)); in ade9000_buffer_postdisable()
1566 struct device *dev = &st->spi->dev; in ade9000_reset()
1576 ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1, in ade9000_reset()
1591 if (!wait_for_completion_timeout(&st->reset_completion, in ade9000_reset()
1594 return -ETIMEDOUT; in ade9000_reset()
1604 struct device *dev = &st->spi->dev; in ade9000_setup()
1607 ret = regmap_multi_reg_write(st->regmap, ade9000_initialization_sequence, in ade9000_setup()
1648 * When using crystal, CLKOUT is connected to crystal and shouldn't in ade9000_setup_clkout()
1651 if (!device_property_present(dev, "#clock-cells") || !st->clkin) in ade9000_setup_clkout()
1654 /* CLKOUT passes through CLKIN with divider of 1 */ in ade9000_setup_clkout()
1655 clkout_hw = devm_clk_hw_register_divider(dev, "clkout", __clk_get_name(st->clkin), in ade9000_setup_clkout()
1658 return dev_err_probe(dev, PTR_ERR(clkout_hw), "Failed to register clkout"); in ade9000_setup_clkout()
1673 if (irq == -EINVAL) in ade9000_request_irq()
1688 struct device *dev = &spi->dev; in ade9000_probe()
1696 return -ENOMEM; in ade9000_probe()
1704 st->regmap = regmap; in ade9000_probe()
1705 st->spi = spi; in ade9000_probe()
1707 init_completion(&st->reset_completion); in ade9000_probe()
1721 ret = devm_mutex_init(dev, &st->lock); in ade9000_probe()
1725 /* External CMOS clock input (optional - crystal can be used instead) */ in ade9000_probe()
1726 st->clkin = devm_clk_get_optional_enabled(dev, NULL); in ade9000_probe()
1727 if (IS_ERR(st->clkin)) in ade9000_probe()
1728 return dev_err_probe(dev, PTR_ERR(st->clkin), "Failed to get and enable clkin"); in ade9000_probe()
1734 indio_dev->name = "ade9000"; in ade9000_probe()
1735 indio_dev->info = &ade9000_info; in ade9000_probe()
1736 indio_dev->modes = INDIO_DIRECT_MODE; in ade9000_probe()
1737 indio_dev->setup_ops = &ade9000_buffer_ops; in ade9000_probe()
1739 ret = devm_regulator_get_enable(&spi->dev, "vdd"); in ade9000_probe()
1741 return dev_err_probe(&spi->dev, ret, in ade9000_probe()
1744 indio_dev->channels = ade9000_channels; in ade9000_probe()
1745 indio_dev->num_channels = ARRAY_SIZE(ade9000_channels); in ade9000_probe()
1758 if (ret != -ENODEV && ret >= 0) { in ade9000_probe()
1759 ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1, in ade9000_probe()
1763 } else if (ret < 0 && ret != -ENODEV) { in ade9000_probe()