Lines Matching full:st
130 #define AD9467_CAN_INVERT(st) \
131 (!(st)->info->has_dco || (st)->info->has_dco_invert)
154 struct ad9467_state *st;
186 static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg)
194 ret = spi_write_then_read(st->spi,
204 static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg,
207 st->buf[0] = reg >> 8;
208 st->buf[1] = reg & 0xFF;
209 st->buf[2] = val;
211 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf));
217 struct ad9467_state *st = iio_priv(indio_dev);
221 guard(mutex)(&st->lock);
222 ret = ad9467_spi_write(st, reg, writeval);
225 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
229 ret = ad9467_spi_read(st, reg);
271 static void __ad9467_get_scale(struct ad9467_state *st, int index,
274 const struct ad9467_chip_info *info = st->info;
441 static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2)
443 const struct ad9467_chip_info *info = st->info;
452 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF);
467 __ad9467_get_scale(st, i, val, val2);
472 static int ad9467_set_scale(struct ad9467_state *st, int val, int val2)
474 const struct ad9467_chip_info *info = st->info;
485 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]);
489 guard(mutex)(&st->lock);
490 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF,
495 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
502 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
506 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode);
510 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
514 static int ad9467_testmode_set(struct ad9467_state *st, unsigned int chan,
519 if (st->info->num_channels > 1) {
521 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, BIT(chan));
526 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, test_mode);
530 if (st->info->num_channels > 1) {
532 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX,
533 GENMASK(st->info->num_channels - 1, 0));
538 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
542 static int ad9467_backend_testmode_on(struct ad9467_state *st,
551 ret = iio_backend_data_format_set(st->back, chan, &data);
555 ret = iio_backend_test_pattern_set(st->back, chan, pattern);
559 return iio_backend_chan_enable(st->back, chan);
562 static int ad9467_backend_testmode_off(struct ad9467_state *st,
571 ret = iio_backend_chan_disable(st->back, chan);
575 ret = iio_backend_test_pattern_set(st->back, chan,
580 return iio_backend_data_format_set(st->back, chan, &data);
583 static int ad9647_calibrate_prepare(struct ad9467_state *st)
588 ret = ad9467_outputmode_set(st, st->info->default_output_mode);
592 for (c = 0; c < st->info->num_channels; c++) {
593 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_PN9_SEQ);
597 ret = ad9467_backend_testmode_on(st, c,
606 static int ad9647_calibrate_polarity_set(struct ad9467_state *st,
611 if (st->info->has_dco) {
617 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE,
626 return iio_backend_data_sample_trigger(st->back, trigger);
653 static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val)
658 if (st->info->has_dco) {
659 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY,
660 val | st->info->dco_en);
664 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
668 for (lane = 0; lane < st->info->num_lanes; lane++) {
669 ret = iio_backend_iodelay_set(st->back, lane, val);
677 static int ad9647_calibrate_stop(struct ad9467_state *st)
682 for (c = 0; c < st->info->num_channels; c++) {
683 ret = ad9467_backend_testmode_off(st, c);
687 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_OFF);
692 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
693 return ad9467_outputmode_set(st, mode);
696 static int ad9467_calibrate(struct ad9467_state *st)
703 unsigned int test_points = st->info->test_points;
704 unsigned long sample_rate = clk_get_rate(st->clk);
705 struct device *dev = &st->spi->dev;
710 bitmap_fill(st->calib_map, st->calib_map_size);
712 ret = ad9647_calibrate_prepare(st);
716 ret = ad9647_calibrate_polarity_set(st, invert);
720 for (point = 0; point < st->info->test_points; point++) {
721 ret = ad9467_calibrate_apply(st, point);
725 for (c = 0; c < st->info->num_channels; c++) {
726 ret = iio_backend_chan_status(st->back, c, &stat);
741 if (c == st->info->num_channels - 1)
743 st->calib_map);
748 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points,
755 if (AD9467_CAN_INVERT(st)) {
764 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points,
771 ret = ad9647_calibrate_polarity_set(st, false);
783 if (st->info->has_dco)
790 ret = ad9467_calibrate_apply(st, val);
795 return ad9647_calibrate_stop(st);
802 struct ad9467_state *st = iio_priv(indio_dev);
806 return ad9467_get_scale(st, val, val2);
808 *val = clk_get_rate(st->clk);
816 static int __ad9467_update_clock(struct ad9467_state *st, long r_clk)
820 ret = clk_set_rate(st->clk, r_clk);
824 guard(mutex)(&st->lock);
825 return ad9467_calibrate(st);
832 struct ad9467_state *st = iio_priv(indio_dev);
833 const struct ad9467_chip_info *info = st->info;
840 return ad9467_set_scale(st, val, val2);
842 r_clk = clk_round_rate(st->clk, val);
844 dev_warn(&st->spi->dev,
849 sample_rate = clk_get_rate(st->clk);
860 ret = __ad9467_update_clock(st, r_clk);
873 struct ad9467_state *st = iio_priv(indio_dev);
874 const struct ad9467_chip_info *info = st->info;
878 *vals = (const int *)st->scales;
891 struct ad9467_state *st = iio_priv(indio_dev);
895 for (c = 0; c < st->info->num_channels; c++) {
897 ret = iio_backend_chan_enable(st->back, c);
899 ret = iio_backend_chan_disable(st->back, c);
923 static int ad9467_scale_fill(struct ad9467_state *st)
925 const struct ad9467_chip_info *info = st->info;
928 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales,
929 sizeof(*st->scales), GFP_KERNEL);
930 if (!st->scales)
934 __ad9467_get_scale(st, i, &val1, &val2);
935 st->scales[i][0] = val1;
936 st->scales[i][1] = val2;
957 static int ad9467_iio_backend_get(struct ad9467_state *st)
959 struct device *dev = &st->spi->dev;
962 st->back = devm_iio_backend_get(dev, NULL);
963 if (!IS_ERR(st->back))
966 if (PTR_ERR(st->back) != -ENOENT)
967 return PTR_ERR(st->back);
989 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev,
992 return PTR_ERR_OR_ZERO(st->back);
1000 struct ad9467_state *st = s->private;
1003 for_each_set_bit(bit, &st->info->test_mask, st->info->test_mask_len)
1015 struct ad9467_state *st = chan->st;
1025 ret = iio_backend_debugfs_print_chan_status(st->back, chan->idx,
1046 struct ad9467_state *st = chan->st;
1056 for_each_set_bit(mode, &st->info->test_mask, st->info->test_mask_len) {
1061 if (mode == st->info->test_mask_len)
1064 guard(mutex)(&st->lock);
1071 ret = ad9467_backend_testmode_off(st, chan->idx);
1076 ret = ad9467_testmode_set(st, chan->idx, mode);
1080 out_mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
1081 ret = ad9467_outputmode_set(st, out_mode);
1085 ret = ad9467_outputmode_set(st, st->info->default_output_mode);
1089 ret = ad9467_testmode_set(st, chan->idx, mode);
1095 ret = ad9467_backend_testmode_on(st, chan->idx,
1100 ret = ad9467_backend_testmode_on(st, chan->idx,
1124 struct ad9467_state *st = file->private_data;
1130 guard(mutex)(&st->lock);
1134 for (bit = 0; bit < st->calib_map_size; bit++) {
1135 if (AD9467_CAN_INVERT(st) && bit == st->calib_map_size / 2)
1139 test_bit(bit, st->calib_map) ? 'x' : 'o');
1157 struct ad9467_state *st = iio_priv(indio_dev);
1164 st->chan_test = devm_kcalloc(&st->spi->dev, st->info->num_channels,
1165 sizeof(*st->chan_test), GFP_KERNEL);
1166 if (!st->chan_test)
1169 debugfs_create_file("calibration_table_dump", 0400, d, st,
1172 for (chan = 0; chan < st->info->num_channels; chan++) {
1175 st->chan_test[chan].idx = chan;
1176 st->chan_test[chan].st = st;
1177 debugfs_create_file(attr_name, 0600, d, &st->chan_test[chan],
1181 debugfs_create_file("in_voltage_test_mode_available", 0400, d, st,
1184 iio_backend_debugfs_add(st->back, indio_dev);
1190 struct ad9467_state *st;
1194 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1198 st = iio_priv(indio_dev);
1199 st->spi = spi;
1201 st->info = spi_get_device_match_data(spi);
1202 if (!st->info)
1205 st->calib_map_size = st->info->test_points;
1206 if (AD9467_CAN_INVERT(st))
1207 st->calib_map_size *= 2;
1209 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
1210 if (IS_ERR(st->clk))
1211 return PTR_ERR(st->clk);
1213 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
1215 if (IS_ERR(st->pwrdown_gpio))
1216 return PTR_ERR(st->pwrdown_gpio);
1222 ret = ad9467_scale_fill(st);
1226 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID);
1227 if (id != st->info->id) {
1229 id, st->info->id);
1233 if (st->info->num_scales > 1)
1237 indio_dev->name = st->info->name;
1238 indio_dev->channels = st->info->channels;
1239 indio_dev->num_channels = st->info->num_channels;
1241 ret = ad9467_iio_backend_get(st);
1245 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev);
1249 ret = devm_iio_backend_enable(&spi->dev, st->back);
1253 ret = ad9467_calibrate(st);