Lines Matching full:conversion

33 	/* Normal mode max conversion time (t_{CONV}). */
35 	/* TURBO mode max conversion time (t_{CONV}). */
93 /* minimum CNV high time to trigger conversion */
122  * @_bits: The number of bits in the conversion result
194 	 * conversion, so place CNV low for t_QUIET to prepare for this.  in ad7944_3wire_cs_mode_init_msg()
200 	 * CS has to be high for full conversion time to avoid triggering the  in ad7944_3wire_cs_mode_init_msg()
225 	 * CS has to be high for full conversion time to avoid triggering the  in ad7944_4wire_mode_init_msg()
257 	 * to be high during the transfer to trigger the conversion.  in ad7944_chain_mode_init_msg()
263 	/* CNV has to be high for full conversion time before reading data. */  in ad7944_chain_mode_init_msg()
278  * during the conversion phase instead of the acquisition phase when reading
281  * high enough SCLK rate to read the sample during the conversion phase.
292 	 * conversion, so place CNV low for t_QUIET to prepare for this.  in ad7944_3wire_cs_mode_init_offload_msg()
296 	/* CNV has to be high for a minimum time to trigger conversion. */  in ad7944_3wire_cs_mode_init_offload_msg()
301 	/* Then we can read the previous sample during the conversion phase */  in ad7944_3wire_cs_mode_init_offload_msg()
319  * ad7944_convert_and_acquire - Perform a single conversion and acquisition
323  * Perform a conversion and acquisition of a single sample using the
326  * Upon successful return adc->sample.raw will contain the conversion result
334 	 * In 4-wire mode, the CNV line is held high for the entire conversion  in ad7944_convert_and_acquire()