231 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_set_syscalib_mode()  local
233 	st->syscalib_mode[chan->channel] = mode;  in ad7192_set_syscalib_mode()
241 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_get_syscalib_mode()  local
243 	return st->syscalib_mode[chan->channel];  in ad7192_get_syscalib_mode()
251 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_write_syscalib()  local
259 	temp = st->syscalib_mode[chan->channel];  in ad7192_write_syscalib()
262 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,  in ad7192_write_syscalib()
265 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,  in ad7192_write_syscalib()
299 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_set_channel()  local
301 	st->conf &= ~AD7192_CONF_CHAN_MASK;  in ad7192_set_channel()
302 	st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);  in ad7192_set_channel()
304 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_channel()
310 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_set_mode()  local
312 	st->mode &= ~AD7192_MODE_SEL_MASK;  in ad7192_set_mode()
313 	st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);  in ad7192_set_mode()
315 	return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_mode()
320 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_append_status()  local
321 	unsigned int mode = st->mode;  in ad7192_append_status()
327 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);  in ad7192_append_status()
331 	st->mode = mode;  in ad7192_append_status()
338 	struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);  in ad7192_disable_all()  local
339 	u32 conf = st->conf;  in ad7192_disable_all()
344 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_disable_all()
348 	st->conf = conf;  in ad7192_disable_all()
391 static int ad7192_calibrate_all(struct ad7192_state *st)  in ad7192_calibrate_all()  argument
393 	return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,  in ad7192_calibrate_all()
426 	struct ad7192_state *st = clk_hw_to_ad7192(hw);  in ad7192_clk_output_is_enabled()  local
428 	return st->clock_sel == AD7192_CLK_INT_CO;  in ad7192_clk_output_is_enabled()
433 	struct ad7192_state *st = clk_hw_to_ad7192(hw);  in ad7192_clk_prepare()  local
436 	st->mode &= ~AD7192_MODE_CLKSRC_MASK;  in ad7192_clk_prepare()
437 	st->mode |= AD7192_CLK_INT_CO;  in ad7192_clk_prepare()
439 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_clk_prepare()
443 	st->clock_sel = AD7192_CLK_INT_CO;  in ad7192_clk_prepare()
450 	struct ad7192_state *st = clk_hw_to_ad7192(hw);  in ad7192_clk_unprepare()  local
453 	st->mode &= ~AD7192_MODE_CLKSRC_MASK;  in ad7192_clk_unprepare()
454 	st->mode |= AD7192_CLK_INT;  in ad7192_clk_unprepare()
456 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_clk_unprepare()
460 	st->clock_sel = AD7192_CLK_INT;  in ad7192_clk_unprepare()
470 static int ad7192_register_clk_provider(struct ad7192_state *st)  in ad7192_register_clk_provider()  argument
472 	struct device *dev = &st->sd.spi->dev;  in ad7192_register_clk_provider()
489 	st->int_clk_hw.init = &init;  in ad7192_register_clk_provider()
490 	ret = devm_clk_hw_register(dev, &st->int_clk_hw);  in ad7192_register_clk_provider()
495 					   &st->int_clk_hw);  in ad7192_register_clk_provider()
498 static int ad7192_clock_setup(struct ad7192_state *st)  in ad7192_clock_setup()  argument
500 	struct device *dev = &st->sd.spi->dev;  in ad7192_clock_setup()
510 		st->clock_sel = AD7192_CLK_INT_CO;  in ad7192_clock_setup()
511 		st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_clock_setup()
517 		st->clock_sel = AD7192_CLK_EXT_MCLK1_2;  in ad7192_clock_setup()
518 		st->mclk = devm_clk_get_enabled(dev, "mclk");  in ad7192_clock_setup()
519 		if (IS_ERR(st->mclk))  in ad7192_clock_setup()
520 			return dev_err_probe(dev, PTR_ERR(st->mclk),  in ad7192_clock_setup()
523 		st->fclk = clk_get_rate(st->mclk);  in ad7192_clock_setup()
524 		if (!ad7192_valid_external_frequency(st->fclk))  in ad7192_clock_setup()
536 		st->clock_sel = AD7192_CLK_INT;  in ad7192_clock_setup()
537 		st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_clock_setup()
539 		ret = ad7192_register_clk_provider(st);  in ad7192_clock_setup()
546 	st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;  in ad7192_clock_setup()
548 	st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);  in ad7192_clock_setup()
549 	if (IS_ERR(st->mclk))  in ad7192_clock_setup()
550 		return dev_err_probe(dev, PTR_ERR(st->mclk),  in ad7192_clock_setup()
553 	st->fclk = clk_get_rate(st->mclk);  in ad7192_clock_setup()
554 	if (!ad7192_valid_external_frequency(st->fclk))  in ad7192_clock_setup()
563 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_setup()  local
570 	ret = ad_sd_reset(&st->sd);  in ad7192_setup()
576 	ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);  in ad7192_setup()
582 	if (id != st->chip_info->chip_id)  in ad7192_setup()
584 			 id, st->chip_info->chip_id);  in ad7192_setup()
586 	st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |  in ad7192_setup()
587 		FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |  in ad7192_setup()
590 	st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);  in ad7192_setup()
594 		st->mode |= AD7192_MODE_REJ60;  in ad7192_setup()
597 	if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)  in ad7192_setup()
598 		st->conf |= AD7192_CONF_REFSEL;  in ad7192_setup()
600 	st->conf &= ~AD7192_CONF_CHOP;  in ad7192_setup()
604 		st->conf |= AD7192_CONF_BUF;  in ad7192_setup()
608 		st->conf |= AD7192_CONF_UNIPOLAR;  in ad7192_setup()
613 		st->conf |= AD7192_CONF_BURN;  in ad7192_setup()
619 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_setup()
623 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_setup()
627 	ret = ad7192_calibrate_all(st);  in ad7192_setup()
632 	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {  in ad7192_setup()
633 		scale_uv = ((u64)st->int_vref_mv * 100000000)  in ad7192_setup()
635 			!FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));  in ad7192_setup()
638 		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;  in ad7192_setup()
639 		st->scale_avail[i][0] = scale_uv;  in ad7192_setup()
642 	st->oversampling_ratio_avail[0] = 1;  in ad7192_setup()
643 	st->oversampling_ratio_avail[1] = 2;  in ad7192_setup()
644 	st->oversampling_ratio_avail[2] = 8;  in ad7192_setup()
645 	st->oversampling_ratio_avail[3] = 16;  in ad7192_setup()
647 	st->filter_freq_avail[0][0] = 600;  in ad7192_setup()
648 	st->filter_freq_avail[1][0] = 800;  in ad7192_setup()
649 	st->filter_freq_avail[2][0] = 2300;  in ad7192_setup()
650 	st->filter_freq_avail[3][0] = 2720;  in ad7192_setup()
652 	st->filter_freq_avail[0][1] = 1000;  in ad7192_setup()
653 	st->filter_freq_avail[1][1] = 1000;  in ad7192_setup()
654 	st->filter_freq_avail[2][1] = 1000;  in ad7192_setup()
655 	st->filter_freq_avail[3][1] = 1000;  in ad7192_setup()
665 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_show_ac_excitation()  local
667 	return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));  in ad7192_show_ac_excitation()
675 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_show_bridge_switch()  local
678 			  FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));  in ad7192_show_bridge_switch()
687 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_set()  local
703 			st->gpocon |= AD7192_GPOCON_BPDSW;  in ad7192_set()
705 			st->gpocon &= ~AD7192_GPOCON_BPDSW;  in ad7192_set()
707 		ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);  in ad7192_set()
711 			st->conf |= AD7192_CONF_ACX;  in ad7192_set()
713 			st->conf &= ~AD7192_CONF_ACX;  in ad7192_set()
715 		ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set()
726 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)  in ad7192_compute_f_order()  argument
730 	avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);  in ad7192_compute_f_order()
735 	oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];  in ad7192_compute_f_order()
743 static int ad7192_get_f_order(struct ad7192_state *st)  in ad7192_get_f_order()  argument
747 	sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);  in ad7192_get_f_order()
748 	chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);  in ad7192_get_f_order()
750 	return ad7192_compute_f_order(st, sinc3_en, chop_en);  in ad7192_get_f_order()
753 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,  in ad7192_compute_f_adc()  argument
756 	unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);  in ad7192_compute_f_adc()
758 	return DIV_ROUND_CLOSEST(st->fclk,  in ad7192_compute_f_adc()
759 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));  in ad7192_compute_f_adc()
762 static int ad7192_get_f_adc(struct ad7192_state *st)  in ad7192_get_f_adc()  argument
764 	unsigned int f_order = ad7192_get_f_order(st);  in ad7192_get_f_adc()
766 	return DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_f_adc()
767 				 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));  in ad7192_get_f_adc()
770 static void ad7192_update_filter_freq_avail(struct ad7192_state *st)  in ad7192_update_filter_freq_avail()  argument
775 	fadc = ad7192_compute_f_adc(st, false, true);  in ad7192_update_filter_freq_avail()
776 	st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);  in ad7192_update_filter_freq_avail()
778 	fadc = ad7192_compute_f_adc(st, true, true);  in ad7192_update_filter_freq_avail()
779 	st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);  in ad7192_update_filter_freq_avail()
781 	fadc = ad7192_compute_f_adc(st, false, false);  in ad7192_update_filter_freq_avail()
782 	st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);  in ad7192_update_filter_freq_avail()
784 	fadc = ad7192_compute_f_adc(st, true, false);  in ad7192_update_filter_freq_avail()
785 	st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);  in ad7192_update_filter_freq_avail()
820 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,  in ad7192_set_3db_filter_freq()  argument
830 	for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {  in ad7192_set_3db_filter_freq()
831 		diff_new = abs(freq - st->filter_freq_avail[i][0]);  in ad7192_set_3db_filter_freq()
840 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
842 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
845 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
847 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
850 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
852 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
855 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
857 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
861 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_3db_filter_freq()
865 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_3db_filter_freq()
868 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)  in ad7192_get_3db_filter_freq()  argument
872 	fadc = ad7192_get_f_adc(st);  in ad7192_get_3db_filter_freq()
874 	if (FIELD_GET(AD7192_CONF_CHOP, st->conf))  in ad7192_get_3db_filter_freq()
876 	if (FIELD_GET(AD7192_MODE_SINC3, st->mode))  in ad7192_get_3db_filter_freq()
888 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_read_raw()  local
889 	bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);  in ad7192_read_raw()
890 	u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);  in ad7192_read_raw()
898 			mutex_lock(&st->lock);  in ad7192_read_raw()
899 			*val = st->scale_avail[gain][0];  in ad7192_read_raw()
900 			*val2 = st->scale_avail[gain][1];  in ad7192_read_raw()
901 			mutex_unlock(&st->lock);  in ad7192_read_raw()
922 			if (st->aincom_mv && !chan->differential)  in ad7192_read_raw()
923 				*val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,  in ad7192_read_raw()
924 							      st->scale_avail[gain][1]);  in ad7192_read_raw()
934 		*val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);  in ad7192_read_raw()
937 		*val = ad7192_get_3db_filter_freq(st);  in ad7192_read_raw()
941 		*val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];  in ad7192_read_raw()
954 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_write_raw()  local
962 	mutex_lock(&st->lock);  in ad7192_write_raw()
967 		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)  in ad7192_write_raw()
968 			if (val2 == st->scale_avail[i][1]) {  in ad7192_write_raw()
970 				tmp = st->conf;  in ad7192_write_raw()
971 				st->conf &= ~AD7192_CONF_GAIN_MASK;  in ad7192_write_raw()
972 				st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);  in ad7192_write_raw()
973 				if (tmp == st->conf)  in ad7192_write_raw()
975 				ad_sd_write_reg(&st->sd, AD7192_REG_CONF,  in ad7192_write_raw()
976 						3, st->conf);  in ad7192_write_raw()
977 				ad7192_calibrate_all(st);  in ad7192_write_raw()
987 		div = st->fclk / (val * ad7192_get_f_order(st) * 1024);  in ad7192_write_raw()
993 		st->mode &= ~AD7192_MODE_RATE_MASK;  in ad7192_write_raw()
994 		st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);  in ad7192_write_raw()
995 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_write_raw()
996 		ad7192_update_filter_freq_avail(st);  in ad7192_write_raw()
999 		ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);  in ad7192_write_raw()
1003 		for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)  in ad7192_write_raw()
1004 			if (val == st->oversampling_ratio_avail[i]) {  in ad7192_write_raw()
1006 				tmp = st->mode;  in ad7192_write_raw()
1007 				st->mode &= ~AD7192_MODE_AVG_MASK;  in ad7192_write_raw()
1008 				st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);  in ad7192_write_raw()
1009 				if (tmp == st->mode)  in ad7192_write_raw()
1011 				ad_sd_write_reg(&st->sd, AD7192_REG_MODE,  in ad7192_write_raw()
1012 						3, st->mode);  in ad7192_write_raw()
1015 		ad7192_update_filter_freq_avail(st);  in ad7192_write_raw()
1021 	mutex_unlock(&st->lock);  in ad7192_write_raw()
1051 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_read_avail()  local
1055 		*vals = (int *)st->scale_avail;  in ad7192_read_avail()
1058 		*length = ARRAY_SIZE(st->scale_avail) * 2;  in ad7192_read_avail()
1062 		*vals = (int *)st->filter_freq_avail;  in ad7192_read_avail()
1064 		*length = ARRAY_SIZE(st->filter_freq_avail) * 2;  in ad7192_read_avail()
1068 		*vals = (int *)st->oversampling_ratio_avail;  in ad7192_read_avail()
1070 		*length = ARRAY_SIZE(st->oversampling_ratio_avail);  in ad7192_read_avail()
1080 	struct ad7192_state *st = iio_priv(indio_dev);  in ad7192_update_scan_mode()  local
1081 	u32 conf = st->conf;  in ad7192_update_scan_mode()
1089 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);  in ad7192_update_scan_mode()
1093 	st->conf = conf;  in ad7192_update_scan_mode()
1334 	struct ad7192_state *st;  in ad7192_probe()  local
1341 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in ad7192_probe()
1345 	st = iio_priv(indio_dev);  in ad7192_probe()
1347 	mutex_init(&st->lock);  in ad7192_probe()
1358 	st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;  in ad7192_probe()
1396 	st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;  in ad7192_probe()
1398 	st->chip_info = spi_get_device_match_data(spi);  in ad7192_probe()
1399 	if (!st->chip_info)  in ad7192_probe()
1402 	indio_dev->name = st->chip_info->name;  in ad7192_probe()
1404 	indio_dev->info = st->chip_info->info;  in ad7192_probe()
1405 	if (st->chip_info->parse_channels) {  in ad7192_probe()
1406 		ret = st->chip_info->parse_channels(indio_dev);  in ad7192_probe()
1410 		indio_dev->channels = st->chip_info->channels;  in ad7192_probe()
1411 		indio_dev->num_channels = st->chip_info->num_channels;  in ad7192_probe()
1414 	ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);  in ad7192_probe()
1422 	ret = ad7192_clock_setup(st);  in ad7192_probe()