Lines Matching +full:gain +full:- +full:milli
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
11 #include <linux/clk-provider.h>
35 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
36 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
38 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
39 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
40 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
41 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
42 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
43 /* (AD7792)/24-bit (AD7192)) */
44 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
45 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
81 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
82 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
83 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
84 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
85 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
106 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */
108 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
111 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
112 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
113 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
114 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
115 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
117 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
118 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
119 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
120 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
122 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
123 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
124 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
125 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
126 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
127 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
128 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
129 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
130 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
131 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
133 #define AD7194_CH_POS(x) (((x) - 1) << 4)
134 #define AD7194_CH_NEG(x) ((x) - 1)
155 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
233 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
243 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
259 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
262 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
263 chan->address); in ad7192_write_syscalib()
265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
266 chan->address); in ad7192_write_syscalib()
301 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
302 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); in ad7192_set_channel()
304 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
312 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
313 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); in ad7192_set_mode()
315 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
321 unsigned int mode = st->mode; in ad7192_append_status()
327 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
331 st->mode = mode; in ad7192_append_status()
339 u32 conf = st->conf; in ad7192_disable_all()
344 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
348 st->conf = conf; in ad7192_disable_all()
391 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
426 return st->clock_sel == AD7192_CLK_INT_CO; in ad7192_clk_output_is_enabled()
434 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_prepare()
435 st->mode |= AD7192_CLK_INT_CO; in ad7192_clk_prepare()
437 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_prepare()
441 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clk_prepare()
451 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_unprepare()
452 st->mode |= AD7192_CLK_INT; in ad7192_clk_unprepare()
454 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_unprepare()
458 st->clock_sel = AD7192_CLK_INT; in ad7192_clk_unprepare()
470 struct device *dev = &st->sd.spi->dev; in ad7192_register_clk_provider()
477 if (!device_property_present(dev, "#clock-cells")) in ad7192_register_clk_provider()
480 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", in ad7192_register_clk_provider()
483 return -ENOMEM; in ad7192_register_clk_provider()
487 st->int_clk_hw.init = &init; in ad7192_register_clk_provider()
488 ret = devm_clk_hw_register(dev, &st->int_clk_hw); in ad7192_register_clk_provider()
493 &st->int_clk_hw); in ad7192_register_clk_provider()
498 struct device *dev = &st->sd.spi->dev; in ad7192_clock_setup()
507 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) { in ad7192_clock_setup()
508 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clock_setup()
509 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
510 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n"); in ad7192_clock_setup()
514 if (device_property_read_bool(dev, "adi,clock-xtal")) { in ad7192_clock_setup()
515 st->clock_sel = AD7192_CLK_EXT_MCLK1_2; in ad7192_clock_setup()
516 st->mclk = devm_clk_get_enabled(dev, "mclk"); in ad7192_clock_setup()
517 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
518 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
521 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
522 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
523 return dev_err_probe(dev, -EINVAL, in ad7192_clock_setup()
526 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n"); in ad7192_clock_setup()
530 ret = device_property_match_property_string(dev, "clock-names", in ad7192_clock_setup()
534 st->clock_sel = AD7192_CLK_INT; in ad7192_clock_setup()
535 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
544 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; in ad7192_clock_setup()
546 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); in ad7192_clock_setup()
547 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
548 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
551 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
552 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
553 return dev_err_probe(dev, -EINVAL, in ad7192_clock_setup()
568 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
574 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
580 if (id != st->chip_info->chip_id) in ad7192_setup()
582 id, st->chip_info->chip_id); in ad7192_setup()
584 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | in ad7192_setup()
585 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | in ad7192_setup()
588 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); in ad7192_setup()
590 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable"); in ad7192_setup()
592 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
594 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable"); in ad7192_setup()
595 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
596 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
598 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
600 buf_en = device_property_read_bool(dev, "adi,buffer-enable"); in ad7192_setup()
602 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
606 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
609 "adi,burnout-currents-enable"); in ad7192_setup()
611 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
617 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
621 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
630 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
631 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
632 >> (indio_dev->channels[0].scan_type.realbits - in ad7192_setup()
633 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); in ad7192_setup()
636 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
637 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
640 st->oversampling_ratio_avail[0] = 1; in ad7192_setup()
641 st->oversampling_ratio_avail[1] = 2; in ad7192_setup()
642 st->oversampling_ratio_avail[2] = 8; in ad7192_setup()
643 st->oversampling_ratio_avail[3] = 16; in ad7192_setup()
645 st->filter_freq_avail[0][0] = 600; in ad7192_setup()
646 st->filter_freq_avail[1][0] = 800; in ad7192_setup()
647 st->filter_freq_avail[2][0] = 2300; in ad7192_setup()
648 st->filter_freq_avail[3][0] = 2720; in ad7192_setup()
650 st->filter_freq_avail[0][1] = 1000; in ad7192_setup()
651 st->filter_freq_avail[1][1] = 1000; in ad7192_setup()
652 st->filter_freq_avail[2][1] = 1000; in ad7192_setup()
653 st->filter_freq_avail[3][1] = 1000; in ad7192_setup()
665 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); in ad7192_show_ac_excitation()
676 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); in ad7192_show_bridge_switch()
698 switch ((u32)this_attr->address) { in ad7192_set()
701 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
703 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
705 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
709 st->conf |= AD7192_CONF_ACX; in ad7192_set()
711 st->conf &= ~AD7192_CONF_ACX; in ad7192_set()
713 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set()
716 ret = -EINVAL; in ad7192_set()
728 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); in ad7192_compute_f_order()
733 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; in ad7192_compute_f_order()
736 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
738 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
745 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); in ad7192_get_f_order()
746 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); in ad7192_get_f_order()
756 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
757 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_compute_f_adc()
764 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
765 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_get_f_adc()
774 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
777 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
780 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); in ad7192_update_filter_freq_avail()
783 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); in ad7192_update_filter_freq_avail()
828 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { in ad7192_set_3db_filter_freq()
829 diff_new = abs(freq - st->filter_freq_avail[i][0]); in ad7192_set_3db_filter_freq()
838 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
840 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
843 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
845 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
848 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
850 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
853 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
855 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
859 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
863 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
872 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) in ad7192_get_3db_filter_freq()
874 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) in ad7192_get_3db_filter_freq()
887 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); in ad7192_read_raw()
888 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); in ad7192_read_raw() local
894 switch (chan->type) { in ad7192_read_raw()
896 mutex_lock(&st->lock); in ad7192_read_raw()
897 *val = st->scale_avail[gain][0]; in ad7192_read_raw()
898 *val2 = st->scale_avail[gain][1]; in ad7192_read_raw()
899 mutex_unlock(&st->lock); in ad7192_read_raw()
906 return -EINVAL; in ad7192_read_raw()
910 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
914 switch (chan->type) { in ad7192_read_raw()
917 * Only applies to pseudo-differential inputs. in ad7192_read_raw()
920 if (st->aincom_mv && !chan->differential) in ad7192_read_raw()
921 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, in ad7192_read_raw()
922 st->scale_avail[gain][1]); in ad7192_read_raw()
926 *val -= 273 * ad7192_get_temp_scale(unipolar); in ad7192_read_raw()
929 return -EINVAL; in ad7192_read_raw()
939 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; in ad7192_read_raw()
943 return -EINVAL; in ad7192_read_raw()
960 mutex_lock(&st->lock); in ad7192_write_raw()
964 ret = -EINVAL; in ad7192_write_raw()
965 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
966 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
968 tmp = st->conf; in ad7192_write_raw()
969 st->conf &= ~AD7192_CONF_GAIN_MASK; in ad7192_write_raw()
970 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); in ad7192_write_raw()
971 if (tmp == st->conf) in ad7192_write_raw()
973 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
974 3, st->conf); in ad7192_write_raw()
981 ret = -EINVAL; in ad7192_write_raw()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in ad7192_write_raw()
987 ret = -EINVAL; in ad7192_write_raw()
991 st->mode &= ~AD7192_MODE_RATE_MASK; in ad7192_write_raw()
992 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); in ad7192_write_raw()
993 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
1000 ret = -EINVAL; in ad7192_write_raw()
1001 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) in ad7192_write_raw()
1002 if (val == st->oversampling_ratio_avail[i]) { in ad7192_write_raw()
1004 tmp = st->mode; in ad7192_write_raw()
1005 st->mode &= ~AD7192_MODE_AVG_MASK; in ad7192_write_raw()
1006 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); in ad7192_write_raw()
1007 if (tmp == st->mode) in ad7192_write_raw()
1009 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, in ad7192_write_raw()
1010 3, st->mode); in ad7192_write_raw()
1016 ret = -EINVAL; in ad7192_write_raw()
1019 mutex_unlock(&st->lock); in ad7192_write_raw()
1040 return -EINVAL; in ad7192_write_raw_get_fmt()
1053 *vals = (int *)st->scale_avail; in ad7192_read_avail()
1056 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
1060 *vals = (int *)st->filter_freq_avail; in ad7192_read_avail()
1062 *length = ARRAY_SIZE(st->filter_freq_avail) * 2; in ad7192_read_avail()
1066 *vals = (int *)st->oversampling_ratio_avail; in ad7192_read_avail()
1068 *length = ARRAY_SIZE(st->oversampling_ratio_avail); in ad7192_read_avail()
1073 return -EINVAL; in ad7192_read_avail()
1079 u32 conf = st->conf; in ad7192_update_scan_mode()
1087 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
1091 st->conf = conf; in ad7192_update_scan_mode()
1128 .differential = ((_channel2) == -1 ? 0 : 1), \
1158 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1162 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1173 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1212 struct device *dev = indio_dev->dev.parent; in ad7194_parse_channels()
1224 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", in ad7194_parse_channels()
1232 return -ENOMEM; in ad7194_parse_channels()
1234 indio_dev->channels = ad7194_channels; in ad7194_parse_channels()
1235 indio_dev->num_channels = num_channels; in ad7194_parse_channels()
1238 ret = fwnode_property_read_u32_array(child, "diff-channels", in ad7194_parse_channels()
1242 return dev_err_probe(dev, -EINVAL, in ad7194_parse_channels()
1247 return dev_err_probe(dev, -EINVAL, in ad7194_parse_channels()
1252 ad7194_channels->scan_index = index++; in ad7194_parse_channels()
1253 ad7194_channels->channel = ain[0]; in ad7194_parse_channels()
1254 ad7194_channels->channel2 = ain[1]; in ad7194_parse_channels()
1255 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); in ad7194_parse_channels()
1257 ret = fwnode_property_read_u32(child, "single-channel", in ad7194_parse_channels()
1264 return dev_err_probe(dev, -EINVAL, in ad7194_parse_channels()
1269 ad7194_channels->scan_index = index++; in ad7194_parse_channels()
1270 ad7194_channels->channel = ain[0]; in ad7194_parse_channels()
1271 ad7194_channels->address = AD7194_CH(ain[0]); in ad7194_parse_channels()
1277 ad7194_channels->scan_index = index++; in ad7194_parse_channels()
1278 ad7194_channels->address = AD7194_CH_TEMP; in ad7194_parse_channels()
1282 ad7194_channels->scan_index = index; in ad7194_parse_channels()
1331 struct device *dev = &spi->dev; in ad7192_probe()
1336 if (!spi->irq) in ad7192_probe()
1337 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n"); in ad7192_probe()
1341 return -ENOMEM; in ad7192_probe()
1345 mutex_init(&st->lock); in ad7192_probe()
1353 if (ret < 0 && ret != -ENODEV) in ad7192_probe()
1356 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; in ad7192_probe()
1360 if (ret == -ENODEV || ret == -EINVAL) { in ad7192_probe()
1364 * We get -EINVAL if avdd is a supply with unknown voltage. We in ad7192_probe()
1375 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI; in ad7192_probe()
1382 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable. in ad7192_probe()
1386 if (ret == -ENODEV) { in ad7192_probe()
1388 return dev_err_probe(dev, -ENODEV, in ad7192_probe()
1394 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; in ad7192_probe()
1396 st->chip_info = spi_get_device_match_data(spi); in ad7192_probe()
1397 if (!st->chip_info) in ad7192_probe()
1398 return -ENODEV; in ad7192_probe()
1400 indio_dev->name = st->chip_info->name; in ad7192_probe()
1401 indio_dev->modes = INDIO_DIRECT_MODE; in ad7192_probe()
1402 indio_dev->info = st->chip_info->info; in ad7192_probe()
1403 if (st->chip_info->parse_channels) { in ad7192_probe()
1404 ret = st->chip_info->parse_channels(indio_dev); in ad7192_probe()
1408 indio_dev->channels = st->chip_info->channels; in ad7192_probe()
1409 indio_dev->num_channels = st->chip_info->num_channels; in ad7192_probe()
1412 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); in ad7192_probe()