1 // SPDX-License-Identifier: GPL-2.0-only
3  * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips
30 #include <linux/spi/spi.h>
33 #include <dt-bindings/iio/adi,ad4695.h>
124 	struct spi_device *spi;  member
189 	.name = "ad4695-8",
219 	.name = "ad4695-16",
296  * ad4695_set_single_cycle_mode - Set the device in single cycle mode
312 	ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL,  in ad4695_set_single_cycle_mode()
318 	ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0),  in ad4695_set_single_cycle_mode()
323 	return regmap_set_bits(st->regmap, AD4695_REG_SETUP,  in ad4695_set_single_cycle_mode()
329  * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode
331  * @n: The number of slots to use - must be >= 2, <= 128
334  * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1
343 	ret = regmap_update_bits(st->regmap, AD4695_REG_SEQ_CTRL,  in ad4695_enter_advanced_sequencer_mode()
347 		FIELD_PREP(AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, n - 1));  in ad4695_enter_advanced_sequencer_mode()
351 	return regmap_update_bits(st->regmap, AD4695_REG_SETUP,  in ad4695_enter_advanced_sequencer_mode()
358  * ad4695_exit_conversion_mode - Exit conversion mode
361  * Sends SPI command to exit conversion mode.
368 		.tx_buf = &st->cnv_cmd2,  in ad4695_exit_conversion_mode()
375 	 * Technically, could do a 5-bit transfer, but shifting to start of  in ad4695_exit_conversion_mode()
376 	 * 8 bits instead for better SPI controller support.  in ad4695_exit_conversion_mode()
378 	st->cnv_cmd2 = AD4695_CMD_EXIT_CNV_MODE << 3;  in ad4695_exit_conversion_mode()
380 	return spi_sync_transfer(st->spi, &xfer, 1);  in ad4695_exit_conversion_mode()
398 		return -EINVAL;  in ad4695_set_ref_voltage()
400 	return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL,  in ad4695_set_ref_voltage()
408 	u32 mask, val;  in ad4695_write_chn_cfg()  local
410 	mask = AD4695_REG_CONFIG_IN_MODE;  in ad4695_write_chn_cfg()
411 	val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0);  in ad4695_write_chn_cfg()
413 	mask |= AD4695_REG_CONFIG_IN_PAIR;  in ad4695_write_chn_cfg()
414 	val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing);  in ad4695_write_chn_cfg()
416 	mask |= AD4695_REG_CONFIG_IN_AINHIGHZ_EN;  in ad4695_write_chn_cfg()
418 			  cfg->highz_en ? 1 : 0);  in ad4695_write_chn_cfg()
420 	return regmap_update_bits(st->regmap,  in ad4695_write_chn_cfg()
421 				  AD4695_REG_CONFIG_IN(cfg->channel),  in ad4695_write_chn_cfg()
422 				  mask, val);  in ad4695_write_chn_cfg()
429 	u8 temp_chan_bit = st->chip_info->num_voltage_inputs;  in ad4695_buffer_preenable()
438 	 * account for the gap between trigger polls - we don't read data from  in ad4695_buffer_preenable()
444 	memset(st->buf_read_xfer, 0, sizeof(st->buf_read_xfer));  in ad4695_buffer_preenable()
447 	xfer = &st->buf_read_xfer[0];  in ad4695_buffer_preenable()
448 	xfer->cs_change = 1;  in ad4695_buffer_preenable()
449 	xfer->delay.value = st->chip_info->t_acq_ns;  in ad4695_buffer_preenable()
450 	xfer->delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
451 	xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;  in ad4695_buffer_preenable()
452 	xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
456 		xfer = &st->buf_read_xfer[num_xfer];  in ad4695_buffer_preenable()
457 		xfer->bits_per_word = 16;  in ad4695_buffer_preenable()
458 		xfer->rx_buf = &st->buf[rx_buf_offset];  in ad4695_buffer_preenable()
459 		xfer->len = 2;  in ad4695_buffer_preenable()
460 		rx_buf_offset += xfer->len;  in ad4695_buffer_preenable()
465 			ret = regmap_write(st->regmap,  in ad4695_buffer_preenable()
481 		xfer = &st->buf_read_xfer[num_xfer];  in ad4695_buffer_preenable()
482 		xfer->delay.value = AD4695_T_SCK_CNV_DELAY_NS;  in ad4695_buffer_preenable()
483 		xfer->delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
484 		xfer->cs_change = 1;  in ad4695_buffer_preenable()
485 		xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;  in ad4695_buffer_preenable()
486 		xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
503 	 * handle the temperature-only case.  in ad4695_buffer_preenable()
507 		st->buf_read_xfer[num_xfer] = st->buf_read_xfer[num_xfer - 1];  in ad4695_buffer_preenable()
508 		st->buf_read_xfer[num_xfer - 1] = st->buf_read_xfer[num_xfer - 2];  in ad4695_buffer_preenable()
512 		xfer = &st->buf_read_xfer[num_xfer - 3];  in ad4695_buffer_preenable()
514 		xfer->cs_change = 1;  in ad4695_buffer_preenable()
515 		xfer->delay.value = st->chip_info->t_acq_ns;  in ad4695_buffer_preenable()
516 		xfer->delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
517 		xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;  in ad4695_buffer_preenable()
518 		xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;  in ad4695_buffer_preenable()
522 		ret = regmap_write(st->regmap,  in ad4695_buffer_preenable()
534 		xfer = &st->buf_read_xfer[num_xfer - 1];  in ad4695_buffer_preenable()
541 	xfer->cs_change = 0;  in ad4695_buffer_preenable()
548 	ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL,  in ad4695_buffer_preenable()
554 	spi_message_init_with_transfers(&st->buf_read_msg, st->buf_read_xfer,  in ad4695_buffer_preenable()
557 	ret = spi_optimize_message(st->spi, &st->buf_read_msg);  in ad4695_buffer_preenable()
564 		spi_unoptimize_message(&st->buf_read_msg);  in ad4695_buffer_preenable()
578 	spi_unoptimize_message(&st->buf_read_msg);  in ad4695_buffer_postdisable()
591 	struct iio_dev *indio_dev = pf->indio_dev;  in ad4695_trigger_handler()
595 	ret = spi_sync(st->spi, &st->buf_read_msg);  in ad4695_trigger_handler()
599 	iio_push_to_buffers_with_timestamp(indio_dev, st->buf, pf->timestamp);  in ad4695_trigger_handler()
602 	iio_trigger_notify_done(indio_dev->trig);  in ad4695_trigger_handler()
608  * ad4695_read_one_sample - Read a single sample using single-cycle mode
612  * Upon successful return, the sample will be stored in `st->raw_data`.
623 			.tx_buf = &st->cnv_cmd,  in ad4695_read_one_sample()
640 	 * in single-cycle mode, so we have to do an extra conversion to read  in ad4695_read_one_sample()
644 		st->cnv_cmd = AD4695_CMD_TEMP_CHAN << 11;  in ad4695_read_one_sample()
646 		ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));  in ad4695_read_one_sample()
652 	st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11;  in ad4695_read_one_sample()
653 	xfers[0].rx_buf = &st->raw_data;  in ad4695_read_one_sample()
655 	return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));  in ad4695_read_one_sample()
660 			   int *val, int *val2, long mask)  in ad4695_read_raw()  argument
663 	struct ad4695_channel_config *cfg = &st->channels_cfg[chan->scan_index];  in ad4695_read_raw()
664 	u8 realbits = chan->scan_type.realbits;  in ad4695_read_raw()
668 	switch (mask) {  in ad4695_read_raw()
670 		iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {  in ad4695_read_raw()
671 			ret = ad4695_read_one_sample(st, chan->address);  in ad4695_read_raw()
675 			if (chan->scan_type.sign == 's')  in ad4695_read_raw()
676 				*val = sign_extend32(st->raw_data, realbits - 1);  in ad4695_read_raw()
678 				*val = st->raw_data;  in ad4695_read_raw()
684 		switch (chan->type) {  in ad4695_read_raw()
686 			*val = st->vref_mv;  in ad4695_read_raw()
687 			*val2 = chan->scan_type.realbits;  in ad4695_read_raw()
690 			/* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */  in ad4695_read_raw()
691 			*val = st->vref_mv * -556;  in ad4695_read_raw()
695 			return -EINVAL;  in ad4695_read_raw()
698 		switch (chan->type) {  in ad4695_read_raw()
700 			if (cfg->pin_pairing == AD4695_IN_PAIR_COM)  in ad4695_read_raw()
701 				*val = st->com_mv * (1 << realbits) / st->vref_mv;  in ad4695_read_raw()
702 			else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD)  in ad4695_read_raw()
703 				*val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv;  in ad4695_read_raw()
709 			/* T_offset (°C) = -725 mV / (-1.8 mV/°C) */  in ad4695_read_raw()
710 			/* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */  in ad4695_read_raw()
711 			*val = -47513600;  in ad4695_read_raw()
712 			*val2 = st->vref_mv;  in ad4695_read_raw()
715 			return -EINVAL;  in ad4695_read_raw()
718 		switch (chan->type) {  in ad4695_read_raw()
720 			iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {  in ad4695_read_raw()
721 				ret = regmap_read(st->regmap16,  in ad4695_read_raw()
722 					AD4695_REG_GAIN_IN(chan->scan_index),  in ad4695_read_raw()
734 			return -EINVAL;  in ad4695_read_raw()
737 		switch (chan->type) {  in ad4695_read_raw()
739 			iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {  in ad4695_read_raw()
740 				ret = regmap_read(st->regmap16,  in ad4695_read_raw()
741 					AD4695_REG_OFFSET_IN(chan->scan_index),  in ad4695_read_raw()
752 					*val *= -1;  in ad4695_read_raw()
753 					*val2 *= -1;  in ad4695_read_raw()
760 			return -EINVAL;  in ad4695_read_raw()
763 		return -EINVAL;  in ad4695_read_raw()
769 			    int val, int val2, long mask)  in ad4695_write_raw()  argument
774 	iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {  in ad4695_write_raw()
775 		switch (mask) {  in ad4695_write_raw()
777 			switch (chan->type) {  in ad4695_write_raw()
788 				return regmap_write(st->regmap16,  in ad4695_write_raw()
789 					AD4695_REG_GAIN_IN(chan->scan_index),  in ad4695_write_raw()
792 				return -EINVAL;  in ad4695_write_raw()
795 			switch (chan->type) {  in ad4695_write_raw()
799 				else if ((val2 < 0 ? -val : val) < S16_MIN / 4)  in ad4695_write_raw()
803 						-(val * 4 + -val2 * 4 / MICRO),  in ad4695_write_raw()
807 						val * 4 - val2 * 4 / MICRO,  in ad4695_write_raw()
814 				return regmap_write(st->regmap16,  in ad4695_write_raw()
815 					AD4695_REG_OFFSET_IN(chan->scan_index),  in ad4695_write_raw()
818 				return -EINVAL;  in ad4695_write_raw()
821 			return -EINVAL;  in ad4695_write_raw()
830 			     long mask)  in ad4695_read_avail()  argument
844 	switch (mask) {  in ad4695_read_avail()
846 		switch (chan->type) {  in ad4695_read_avail()
852 			return -EINVAL;  in ad4695_read_avail()
855 		switch (chan->type) {  in ad4695_read_avail()
861 			return -EINVAL;  in ad4695_read_avail()
864 		return -EINVAL;  in ad4695_read_avail()
875 	iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {  in ad4695_debugfs_reg_access()
877 			if (regmap_check_range_table(st->regmap, reg,  in ad4695_debugfs_reg_access()
879 				return regmap_read(st->regmap, reg, readval);  in ad4695_debugfs_reg_access()
880 			if (regmap_check_range_table(st->regmap16, reg,  in ad4695_debugfs_reg_access()
882 				return regmap_read(st->regmap16, reg, readval);  in ad4695_debugfs_reg_access()
884 			if (regmap_check_range_table(st->regmap, reg,  in ad4695_debugfs_reg_access()
886 				return regmap_write(st->regmap, reg, writeval);  in ad4695_debugfs_reg_access()
887 			if (regmap_check_range_table(st->regmap16, reg,  in ad4695_debugfs_reg_access()
889 				return regmap_write(st->regmap16, reg, writeval);  in ad4695_debugfs_reg_access()
893 	return -EINVAL;  in ad4695_debugfs_reg_access()
905 	struct device *dev = &st->spi->dev;  in ad4695_parse_channel_cfg()
911 	for (i = 0; i < st->chip_info->num_voltage_inputs; i++) {  in ad4695_parse_channel_cfg()
912 		chan_cfg = &st->channels_cfg[i];  in ad4695_parse_channel_cfg()
913 		iio_chan = &st->iio_chan[i];  in ad4695_parse_channel_cfg()
915 		chan_cfg->highz_en = true;  in ad4695_parse_channel_cfg()
916 		chan_cfg->channel = i;  in ad4695_parse_channel_cfg()
919 		iio_chan->channel = i;  in ad4695_parse_channel_cfg()
920 		iio_chan->scan_index = i;  in ad4695_parse_channel_cfg()
921 		iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i);  in ad4695_parse_channel_cfg()
934 		if (reg >= st->chip_info->num_voltage_inputs)  in ad4695_parse_channel_cfg()
935 			return dev_err_probe(dev, -EINVAL,  in ad4695_parse_channel_cfg()
939 		iio_chan = &st->iio_chan[reg];  in ad4695_parse_channel_cfg()
940 		chan_cfg = &st->channels_cfg[reg];  in ad4695_parse_channel_cfg()
942 		chan_cfg->highz_en =  in ad4695_parse_channel_cfg()
943 			!fwnode_property_read_bool(child, "adi,no-high-z");  in ad4695_parse_channel_cfg()
944 		chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar");  in ad4695_parse_channel_cfg()
946 		ret = fwnode_property_read_u32(child, "common-mode-channel",  in ad4695_parse_channel_cfg()
948 		if (ret && ret != -EINVAL)  in ad4695_parse_channel_cfg()
950 				"failed to read common-mode-channel (%s)\n",  in ad4695_parse_channel_cfg()
953 		if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND)  in ad4695_parse_channel_cfg()
954 			chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND;  in ad4695_parse_channel_cfg()
956 			chan_cfg->pin_pairing = AD4695_IN_PAIR_COM;  in ad4695_parse_channel_cfg()
958 			chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD;  in ad4695_parse_channel_cfg()
960 		if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&  in ad4695_parse_channel_cfg()
962 			return dev_err_probe(dev, -EINVAL,  in ad4695_parse_channel_cfg()
963 				"common-mode-channel must be odd number (%s)\n",  in ad4695_parse_channel_cfg()
966 		if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&  in ad4695_parse_channel_cfg()
968 			return dev_err_probe(dev, -EINVAL,  in ad4695_parse_channel_cfg()
969 				"common-mode-channel must be next consecutive channel (%s)\n",  in ad4695_parse_channel_cfg()
972 		if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) {  in ad4695_parse_channel_cfg()
983 			chan_cfg->common_mode_mv = ret / 1000;  in ad4695_parse_channel_cfg()
986 		if (chan_cfg->bipolar &&  in ad4695_parse_channel_cfg()
987 		    chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND)  in ad4695_parse_channel_cfg()
988 			return dev_err_probe(dev, -EINVAL,  in ad4695_parse_channel_cfg()
992 		if (chan_cfg->bipolar)  in ad4695_parse_channel_cfg()
993 			iio_chan->scan_type.sign = 's';  in ad4695_parse_channel_cfg()
1001 	st->iio_chan[i] = ad4695_temp_channel_template;  in ad4695_parse_channel_cfg()
1002 	st->iio_chan[i].scan_index = i;  in ad4695_parse_channel_cfg()
1005 	st->iio_chan[i] = ad4695_soft_timestamp_channel_template;  in ad4695_parse_channel_cfg()
1006 	st->iio_chan[i].scan_index = i;  in ad4695_parse_channel_cfg()
1011 static int ad4695_probe(struct spi_device *spi)  in ad4695_probe()  argument
1013 	struct device *dev = &spi->dev;  in ad4695_probe()
1026 	/* Driver currently requires CNV pin to be connected to SPI CS */  in ad4695_probe()
1028 		return dev_err_probe(dev, -ENODEV,  in ad4695_probe()
1033 		return -ENOMEM;  in ad4695_probe()
1036 	st->spi = spi;  in ad4695_probe()
1038 	st->chip_info = spi_get_device_match_data(spi);  in ad4695_probe()
1039 	if (!st->chip_info)  in ad4695_probe()
1040 		return -EINVAL;  in ad4695_probe()
1043 	spi->max_speed_hz = AD4695_REG_ACCESS_SCLK_HZ;  in ad4695_probe()
1045 	st->regmap = devm_regmap_init_spi(spi, &ad4695_regmap_config);  in ad4695_probe()
1046 	if (IS_ERR(st->regmap))  in ad4695_probe()
1047 		return dev_err_probe(dev, PTR_ERR(st->regmap),  in ad4695_probe()
1050 	st->regmap16 = devm_regmap_init_spi(spi, &ad4695_regmap16_config);  in ad4695_probe()
1051 	if (IS_ERR(st->regmap16))  in ad4695_probe()
1052 		return dev_err_probe(dev, PTR_ERR(st->regmap16),  in ad4695_probe()
1062 	/* If LDO_IN supply is present, then we are using internal LDO. */  in ad4695_probe()
1063 	ret = devm_regulator_get_enable_optional(dev, "ldo-in");  in ad4695_probe()
1064 	if (ret < 0 && ret != -ENODEV)  in ad4695_probe()
1080 	if (ret < 0 && ret != -ENODEV)  in ad4695_probe()
1083 	if (ret != -ENODEV) {  in ad4695_probe()
1084 		st->vref_mv = ret / 1000;  in ad4695_probe()
1093 		st->vref_mv = ret / 1000;  in ad4695_probe()
1098 	if (ret < 0 && ret != -ENODEV)  in ad4695_probe()
1101 	st->com_mv = ret == -ENODEV ? 0 : ret / 1000;  in ad4695_probe()
1108 	st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);  in ad4695_probe()
1109 	if (IS_ERR(st->reset_gpio))  in ad4695_probe()
1110 		return PTR_ERR(st->reset_gpio);  in ad4695_probe()
1112 	if (st->reset_gpio) {  in ad4695_probe()
1113 		gpiod_set_value(st->reset_gpio, 0);  in ad4695_probe()
1116 		ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A,  in ad4695_probe()
1125 	ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A,  in ad4695_probe()
1131 	ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP,  in ad4695_probe()
1140 	if (device_property_present(dev, "adi,no-ref-current-limit")) {  in ad4695_probe()
1141 		ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,  in ad4695_probe()
1147 	if (device_property_present(dev, "adi,no-ref-high-z")) {  in ad4695_probe()
1149 			return dev_err_probe(dev, -EINVAL,  in ad4695_probe()
1150 				"Cannot disable high-Z mode for internal reference buffer\n");  in ad4695_probe()
1152 		ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL,  in ad4695_probe()
1158 	ret = ad4695_set_ref_voltage(st, st->vref_mv);  in ad4695_probe()
1163 		ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,  in ad4695_probe()
1176 	indio_dev->name = st->chip_info->name;  in ad4695_probe()
1177 	indio_dev->info = &ad4695_info;  in ad4695_probe()
1178 	indio_dev->modes = INDIO_DIRECT_MODE;  in ad4695_probe()
1179 	indio_dev->channels = st->iio_chan;  in ad4695_probe()
1180 	indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2;  in ad4695_probe()
1199 MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table);