Lines Matching +full:common +full:- +full:mode +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/iio/buffer-dmaengine.h>
38 #include <dt-bindings/iio/adc/adi,ad4695.h>
91 /* Conversion mode commands */
124 unsigned int channel; member
152 /* Common mode input pin voltage. */
208 .name = "ad4695-8",
237 .name = "ad4695-16",
254 .tx_buf = st->regmap_bus_data, in ad4695_regmap_bus_reg_write()
257 if (count > ARRAY_SIZE(st->regmap_bus_data)) in ad4695_regmap_bus_reg_write()
258 return -EINVAL; in ad4695_regmap_bus_reg_write()
260 memcpy(st->regmap_bus_data, data, count); in ad4695_regmap_bus_reg_write()
262 return spi_sync_transfer(st->spi, &xfer, 1); in ad4695_regmap_bus_reg_write()
274 .tx_buf = &st->regmap_bus_data[0], in ad4695_regmap_bus_reg_read()
278 .rx_buf = &st->regmap_bus_data[2], in ad4695_regmap_bus_reg_read()
284 return -EINVAL; in ad4695_regmap_bus_reg_read()
287 return -EINVAL; in ad4695_regmap_bus_reg_read()
289 memcpy(&st->regmap_bus_data[0], reg, reg_size); in ad4695_regmap_bus_reg_read()
291 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); in ad4695_regmap_bus_reg_read()
295 memcpy(val, &st->regmap_bus_data[2], val_size); in ad4695_regmap_bus_reg_read()
438 gpiod_set_value_cansleep(st->cnv_gpio, 1); in ad4695_cnv_manual_trigger()
440 gpiod_set_value_cansleep(st->cnv_gpio, 0); in ad4695_cnv_manual_trigger()
444 * ad4695_set_single_cycle_mode - Set the device in single cycle mode
446 * @channel: The first channel to read
448 * As per the datasheet, to enable single cycle mode, we need to set
450 * triggers the first conversion using the channel in AS_SLOT0.
456 unsigned int channel) in ad4695_set_single_cycle_mode() argument
460 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL, in ad4695_set_single_cycle_mode()
466 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0), in ad4695_set_single_cycle_mode()
467 FIELD_PREP(AD4695_REG_AS_SLOT_INX, channel)); in ad4695_set_single_cycle_mode()
471 return regmap_set_bits(st->regmap, AD4695_REG_SETUP, in ad4695_set_single_cycle_mode()
477 * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode
479 * @n: The number of slots to use - must be >= 2, <= 128
482 * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1
483 * triggers the first conversion using the channel in AS_SLOT0.
491 ret = regmap_update_bits(st->regmap, AD4695_REG_SEQ_CTRL, in ad4695_enter_advanced_sequencer_mode()
495 FIELD_PREP(AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, n - 1)); in ad4695_enter_advanced_sequencer_mode()
499 return regmap_update_bits(st->regmap, AD4695_REG_SETUP, in ad4695_enter_advanced_sequencer_mode()
506 * ad4695_exit_conversion_mode - Exit conversion mode
509 * Sends SPI command to exit conversion mode.
535 .tx_buf = &st->cnv_cmd2, in ad4695_exit_conversion_mode()
543 * Technically, could do a 5-bit transfer, but shifting to start of in ad4695_exit_conversion_mode()
546 st->cnv_cmd2 = AD4695_CMD_EXIT_CNV_MODE << 3; in ad4695_exit_conversion_mode()
548 if (st->cnv_gpio) { in ad4695_exit_conversion_mode()
556 return spi_sync_transfer(st->spi, &xfers[1], 1); in ad4695_exit_conversion_mode()
559 return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); in ad4695_exit_conversion_mode()
577 return -EINVAL; in ad4695_set_ref_voltage()
579 return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL, in ad4695_set_ref_voltage()
585 * ad4695_osr_to_regval - convert ratio to OSR register value
592 * Returns: register value (0 to 3) or -EINVAL if there is not an exact
604 return -EINVAL; in ad4695_osr_to_regval()
613 val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0); in ad4695_write_chn_cfg()
616 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing); in ad4695_write_chn_cfg()
620 cfg->highz_en ? 1 : 0); in ad4695_write_chn_cfg()
622 return regmap_update_bits(st->regmap, in ad4695_write_chn_cfg()
623 AD4695_REG_CONFIG_IN(cfg->channel), in ad4695_write_chn_cfg()
631 u8 temp_chan_bit = st->chip_info->num_voltage_inputs; in ad4695_buffer_preenable()
639 * voltage input channel. Slot 0 in the advanced sequencer is used to in ad4695_buffer_preenable()
640 * account for the gap between trigger polls - we don't read data from in ad4695_buffer_preenable()
641 * this slot. Each enabled voltage channel is assigned a slot starting in ad4695_buffer_preenable()
646 memset(st->buf_read_xfer, 0, sizeof(st->buf_read_xfer)); in ad4695_buffer_preenable()
649 xfer = &st->buf_read_xfer[0]; in ad4695_buffer_preenable()
650 xfer->cs_change = 1; in ad4695_buffer_preenable()
651 xfer->delay.value = st->chip_info->t_acq_ns; in ad4695_buffer_preenable()
652 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
653 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; in ad4695_buffer_preenable()
654 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
658 xfer = &st->buf_read_xfer[num_xfer]; in ad4695_buffer_preenable()
659 xfer->bits_per_word = 16; in ad4695_buffer_preenable()
660 xfer->rx_buf = &st->buf[rx_buf_offset++]; in ad4695_buffer_preenable()
661 xfer->len = 2; in ad4695_buffer_preenable()
666 ret = regmap_write(st->regmap, in ad4695_buffer_preenable()
682 xfer = &st->buf_read_xfer[num_xfer]; in ad4695_buffer_preenable()
683 xfer->delay.value = AD4695_T_SCK_CNV_DELAY_NS; in ad4695_buffer_preenable()
684 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
685 xfer->cs_change = 1; in ad4695_buffer_preenable()
686 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; in ad4695_buffer_preenable()
687 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
695 * enabled voltage channel to meet this requirement. If the temperature in ad4695_buffer_preenable()
696 * channel is the only enabled channel, we need to add one more slot in in ad4695_buffer_preenable()
698 * sensor is sampled at the end of the channel sequence in advanced in ad4695_buffer_preenable()
699 * sequencer mode (see datasheet page 38). in ad4695_buffer_preenable()
704 * handle the temperature-only case. in ad4695_buffer_preenable()
708 st->buf_read_xfer[num_xfer] = st->buf_read_xfer[num_xfer - 1]; in ad4695_buffer_preenable()
709 st->buf_read_xfer[num_xfer - 1] = st->buf_read_xfer[num_xfer - 2]; in ad4695_buffer_preenable()
713 xfer = &st->buf_read_xfer[num_xfer - 3]; in ad4695_buffer_preenable()
715 xfer->cs_change = 1; in ad4695_buffer_preenable()
716 xfer->delay.value = st->chip_info->t_acq_ns; in ad4695_buffer_preenable()
717 xfer->delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
718 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS; in ad4695_buffer_preenable()
719 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad4695_buffer_preenable()
723 ret = regmap_write(st->regmap, in ad4695_buffer_preenable()
735 xfer = &st->buf_read_xfer[num_xfer - 1]; in ad4695_buffer_preenable()
742 xfer->cs_change = 0; in ad4695_buffer_preenable()
745 * Temperature channel isn't included in the sequence, but rather in ad4695_buffer_preenable()
749 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL, in ad4695_buffer_preenable()
755 spi_message_init_with_transfers(&st->buf_read_msg, st->buf_read_xfer, in ad4695_buffer_preenable()
758 ret = spi_optimize_message(st->spi, &st->buf_read_msg); in ad4695_buffer_preenable()
765 spi_unoptimize_message(&st->buf_read_msg); in ad4695_buffer_preenable()
779 spi_unoptimize_message(&st->buf_read_msg); in ad4695_buffer_postdisable()
792 struct iio_dev *indio_dev = pf->indio_dev; in ad4695_trigger_handler()
796 ret = spi_sync(st->spi, &st->buf_read_msg); in ad4695_trigger_handler()
800 iio_push_to_buffers_with_ts(indio_dev, st->buf, sizeof(st->buf), in ad4695_trigger_handler()
801 pf->timestamp); in ad4695_trigger_handler()
804 iio_trigger_notify_done(indio_dev->trig); in ad4695_trigger_handler()
815 struct spi_transfer *xfer = &st->buf_read_xfer[0]; in ad4695_offload_buffer_postenable()
817 u8 temp_chan_bit = st->chip_info->num_voltage_inputs; in ad4695_offload_buffer_postenable()
829 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(num_slots), in ad4695_offload_buffer_postenable()
838 * For non-offload, we could discard data to work around this in ad4695_offload_buffer_postenable()
842 dev_err(&st->spi->dev, in ad4695_offload_buffer_postenable()
844 return -EINVAL; in ad4695_offload_buffer_postenable()
847 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL, in ad4695_offload_buffer_postenable()
854 /* Each BUSY event means just one sample for one channel is ready. */ in ad4695_offload_buffer_postenable()
856 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; in ad4695_offload_buffer_postenable()
858 xfer->bits_per_word = 19; in ad4695_offload_buffer_postenable()
859 xfer->len = 4; in ad4695_offload_buffer_postenable()
861 spi_message_init_with_transfers(&st->buf_read_msg, xfer, 1); in ad4695_offload_buffer_postenable()
862 st->buf_read_msg.offload = st->offload; in ad4695_offload_buffer_postenable()
864 ret = spi_optimize_message(st->spi, &st->buf_read_msg); in ad4695_offload_buffer_postenable()
874 ret = regmap_set_bits(st->regmap, AD4695_REG_GP_MODE, in ad4695_offload_buffer_postenable()
879 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, in ad4695_offload_buffer_postenable()
888 mutex_lock(&st->cnv_pwm_lock); in ad4695_offload_buffer_postenable()
889 pwm_get_state(st->cnv_pwm, &state); in ad4695_offload_buffer_postenable()
895 ret = pwm_apply_might_sleep(st->cnv_pwm, &state); in ad4695_offload_buffer_postenable()
896 mutex_unlock(&st->cnv_pwm_lock); in ad4695_offload_buffer_postenable()
908 spi_offload_trigger_disable(st->offload, st->offload_trigger); in ad4695_offload_buffer_postenable()
913 spi_offload_trigger_disable(st->offload, st->offload_trigger); in ad4695_offload_buffer_postenable()
916 regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE, in ad4695_offload_buffer_postenable()
920 spi_unoptimize_message(&st->buf_read_msg); in ad4695_offload_buffer_postenable()
931 scoped_guard(mutex, &st->cnv_pwm_lock) { in ad4695_offload_buffer_predisable()
932 pwm_get_state(st->cnv_pwm, &state); in ad4695_offload_buffer_predisable()
934 ret = pwm_apply_might_sleep(st->cnv_pwm, &state); in ad4695_offload_buffer_predisable()
939 spi_offload_trigger_disable(st->offload, st->offload_trigger); in ad4695_offload_buffer_predisable()
949 ret = regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE, in ad4695_offload_buffer_predisable()
954 spi_unoptimize_message(&st->buf_read_msg); in ad4695_offload_buffer_predisable()
965 * ad4695_read_one_sample - Read a single sample using single-cycle mode
967 * @address: The address of the channel to read
969 * Upon successful return, the sample will be stored in `st->raw_data`.
980 .tx_buf = &st->cnv_cmd, in ad4695_read_one_sample()
999 if (st->cnv_gpio) in ad4695_read_one_sample()
1003 * Setting the first channel to the temperature channel isn't supported in ad4695_read_one_sample()
1004 * in single-cycle mode, so we have to do an extra conversion to read in ad4695_read_one_sample()
1008 st->cnv_cmd = AD4695_CMD_TEMP_CHAN << 11; in ad4695_read_one_sample()
1010 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); in ad4695_read_one_sample()
1018 if (st->cnv_gpio) in ad4695_read_one_sample()
1022 /* Then read the result and exit conversion mode. */ in ad4695_read_one_sample()
1023 st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11; in ad4695_read_one_sample()
1024 xfers[0].rx_buf = &st->raw_data; in ad4695_read_one_sample()
1026 return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); in ad4695_read_one_sample()
1033 u8 realbits = chan->scan_type.realbits; in __ad4695_read_info_raw()
1036 ret = ad4695_read_one_sample(st, chan->address); in __ad4695_read_info_raw()
1040 if (chan->scan_type.sign == 's') in __ad4695_read_info_raw()
1041 *val = sign_extend32(st->raw_data, realbits - 1); in __ad4695_read_info_raw()
1043 *val = st->raw_data; in __ad4695_read_info_raw()
1059 if (chan->type == IIO_VOLTAGE) in ad4695_read_raw()
1060 cfg = &st->channels_cfg[chan->scan_index]; in ad4695_read_raw()
1066 realbits = scan_type->realbits; in ad4695_read_raw()
1071 return -EBUSY; in ad4695_read_raw()
1077 switch (chan->type) { in ad4695_read_raw()
1079 *val = st->vref_mv; in ad4695_read_raw()
1083 /* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */ in ad4695_read_raw()
1084 *val = st->vref_mv * -556; in ad4695_read_raw()
1088 return -EINVAL; in ad4695_read_raw()
1091 switch (chan->type) { in ad4695_read_raw()
1093 if (cfg->pin_pairing == AD4695_IN_PAIR_COM) in ad4695_read_raw()
1094 *val = st->com_mv * (1 << realbits) / st->vref_mv; in ad4695_read_raw()
1095 else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) in ad4695_read_raw()
1096 *val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv; in ad4695_read_raw()
1102 /* T_offset (°C) = -725 mV / (-1.8 mV/°C) */ in ad4695_read_raw()
1103 /* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */ in ad4695_read_raw()
1104 *val = -47513600; in ad4695_read_raw()
1105 *val2 = st->vref_mv; in ad4695_read_raw()
1108 return -EINVAL; in ad4695_read_raw()
1111 switch (chan->type) { in ad4695_read_raw()
1114 return -EBUSY; in ad4695_read_raw()
1115 ret = regmap_read(st->regmap16, in ad4695_read_raw()
1116 AD4695_REG_GAIN_IN(chan->scan_index), in ad4695_read_raw()
1126 return -EINVAL; in ad4695_read_raw()
1129 switch (chan->type) in ad4695_read_raw()
1132 return -EBUSY; in ad4695_read_raw()
1133 ret = regmap_read(st->regmap16, in ad4695_read_raw()
1134 AD4695_REG_OFFSET_IN(chan->scan_index), in ad4695_read_raw()
1142 switch (cfg->oversampling_ratio) { in ad4695_read_raw()
1160 return -EINVAL; in ad4695_read_raw()
1164 *val *= -1; in ad4695_read_raw()
1165 *val2 *= -1; in ad4695_read_raw()
1170 return -EINVAL; in ad4695_read_raw()
1173 switch (chan->type) { in ad4695_read_raw()
1175 *val = cfg->oversampling_ratio; in ad4695_read_raw()
1178 return -EINVAL; in ad4695_read_raw()
1184 if (chan->type == IIO_VOLTAGE) in ad4695_read_raw()
1185 osr = cfg->oversampling_ratio; in ad4695_read_raw()
1187 ret = pwm_get_state_hw(st->cnv_pwm, &state); in ad4695_read_raw()
1192 * The effective sampling frequency for a channel is the input in ad4695_read_raw()
1193 * frequency divided by the channel's OSR value. in ad4695_read_raw()
1200 return -EINVAL; in ad4695_read_raw()
1225 switch (chan->type) { in ad4695_set_osr_val()
1227 st->channels_cfg[chan->scan_index].oversampling_ratio = val; in ad4695_set_osr_val()
1228 return regmap_update_bits(st->regmap, in ad4695_set_osr_val()
1229 AD4695_REG_CONFIG_IN(chan->scan_index), in ad4695_set_osr_val()
1233 return -EINVAL; in ad4695_set_osr_val()
1258 /* val2 range is (-MICRO, MICRO) if val == 0, otherwise [0, MICRO) */ in ad4695_get_calibbias()
1260 val_calc = val * scale - val2 * scale / MICRO; in ad4695_get_calibbias()
1280 if (chan->type == IIO_VOLTAGE) in __ad4695_write_raw()
1281 osr = st->channels_cfg[chan->scan_index].oversampling_ratio; in __ad4695_write_raw()
1285 switch (chan->type) { in __ad4695_write_raw()
1296 return regmap_write(st->regmap16, in __ad4695_write_raw()
1297 AD4695_REG_GAIN_IN(chan->scan_index), in __ad4695_write_raw()
1300 return -EINVAL; in __ad4695_write_raw()
1303 switch (chan->type) { in __ad4695_write_raw()
1306 return regmap_write(st->regmap16, in __ad4695_write_raw()
1307 AD4695_REG_OFFSET_IN(chan->scan_index), in __ad4695_write_raw()
1310 return -EINVAL; in __ad4695_write_raw()
1316 * the channel's oversampling ratio. in __ad4695_write_raw()
1318 u64 max_osr_rate = DIV_ROUND_UP_ULL(st->chip_info->max_sample_rate, in __ad4695_write_raw()
1322 return -EINVAL; in __ad4695_write_raw()
1324 guard(mutex)(&st->cnv_pwm_lock); in __ad4695_write_raw()
1325 pwm_get_state(st->cnv_pwm, &state); in __ad4695_write_raw()
1331 return pwm_apply_might_sleep(st->cnv_pwm, &state); in __ad4695_write_raw()
1336 return -EINVAL; in __ad4695_write_raw()
1347 return -EBUSY; in ad4695_write_raw()
1394 if (chan->type == IIO_VOLTAGE) in ad4695_read_avail()
1395 osr = st->channels_cfg[chan->scan_index].oversampling_ratio; in ad4695_read_avail()
1399 switch (chan->type) { in ad4695_read_avail()
1405 return -EINVAL; in ad4695_read_avail()
1408 switch (chan->type) { in ad4695_read_avail()
1421 return -EINVAL; in ad4695_read_avail()
1424 /* Max sample rate for the channel depends on OSR */ in ad4695_read_avail()
1425 st->sample_freq_range[2] = in ad4695_read_avail()
1426 DIV_ROUND_UP_ULL(st->chip_info->max_sample_rate, osr); in ad4695_read_avail()
1427 *vals = st->sample_freq_range; in ad4695_read_avail()
1431 switch (chan->type) { in ad4695_read_avail()
1438 return -EINVAL; in ad4695_read_avail()
1441 return -EINVAL; in ad4695_read_avail()
1451 int ret = -EINVAL; in ad4695_debugfs_reg_access()
1454 return -EBUSY; in ad4695_debugfs_reg_access()
1457 if (regmap_check_range_table(st->regmap, reg, in ad4695_debugfs_reg_access()
1459 ret = regmap_read(st->regmap, reg, readval); in ad4695_debugfs_reg_access()
1460 if (regmap_check_range_table(st->regmap16, reg, in ad4695_debugfs_reg_access()
1462 ret = regmap_read(st->regmap16, reg, readval); in ad4695_debugfs_reg_access()
1464 if (regmap_check_range_table(st->regmap, reg, in ad4695_debugfs_reg_access()
1466 ret = regmap_write(st->regmap, reg, writeval); in ad4695_debugfs_reg_access()
1467 if (regmap_check_range_table(st->regmap16, reg, in ad4695_debugfs_reg_access()
1469 ret = regmap_write(st->regmap16, reg, writeval); in ad4695_debugfs_reg_access()
1480 unsigned int osr = st->channels_cfg[chan->scan_index].oversampling_ratio; in ad4695_get_current_scan_type()
1492 return -EINVAL; in ad4695_get_current_scan_type()
1515 struct device *dev = &st->spi->dev; in ad4695_parse_channel_cfg()
1521 for (i = 0; i < st->chip_info->num_voltage_inputs; i++) { in ad4695_parse_channel_cfg()
1522 chan_cfg = &st->channels_cfg[i]; in ad4695_parse_channel_cfg()
1523 iio_chan = &st->iio_chan[i]; in ad4695_parse_channel_cfg()
1525 chan_cfg->highz_en = true; in ad4695_parse_channel_cfg()
1526 chan_cfg->channel = i; in ad4695_parse_channel_cfg()
1529 chan_cfg->oversampling_ratio = 1; in ad4695_parse_channel_cfg()
1532 iio_chan->channel = i; in ad4695_parse_channel_cfg()
1533 iio_chan->scan_index = i; in ad4695_parse_channel_cfg()
1534 iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i); in ad4695_parse_channel_cfg()
1547 if (reg >= st->chip_info->num_voltage_inputs) in ad4695_parse_channel_cfg()
1548 return dev_err_probe(dev, -EINVAL, in ad4695_parse_channel_cfg()
1552 iio_chan = &st->iio_chan[reg]; in ad4695_parse_channel_cfg()
1553 chan_cfg = &st->channels_cfg[reg]; in ad4695_parse_channel_cfg()
1555 chan_cfg->highz_en = in ad4695_parse_channel_cfg()
1556 !fwnode_property_read_bool(child, "adi,no-high-z"); in ad4695_parse_channel_cfg()
1557 chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); in ad4695_parse_channel_cfg()
1559 ret = fwnode_property_read_u32(child, "common-mode-channel", in ad4695_parse_channel_cfg()
1561 if (ret && ret != -EINVAL) in ad4695_parse_channel_cfg()
1563 "failed to read common-mode-channel (%s)\n", in ad4695_parse_channel_cfg()
1566 if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND) in ad4695_parse_channel_cfg()
1567 chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND; in ad4695_parse_channel_cfg()
1569 chan_cfg->pin_pairing = AD4695_IN_PAIR_COM; in ad4695_parse_channel_cfg()
1571 chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD; in ad4695_parse_channel_cfg()
1573 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && in ad4695_parse_channel_cfg()
1575 return dev_err_probe(dev, -EINVAL, in ad4695_parse_channel_cfg()
1576 "common-mode-channel must be odd number (%s)\n", in ad4695_parse_channel_cfg()
1579 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && in ad4695_parse_channel_cfg()
1581 return dev_err_probe(dev, -EINVAL, in ad4695_parse_channel_cfg()
1582 "common-mode-channel must be next consecutive channel (%s)\n", in ad4695_parse_channel_cfg()
1585 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) { in ad4695_parse_channel_cfg()
1596 chan_cfg->common_mode_mv = ret / 1000; in ad4695_parse_channel_cfg()
1599 if (chan_cfg->bipolar && in ad4695_parse_channel_cfg()
1600 chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND) in ad4695_parse_channel_cfg()
1601 return dev_err_probe(dev, -EINVAL, in ad4695_parse_channel_cfg()
1602 "bipolar mode is not available for inputs paired with REFGND (%s).\n", in ad4695_parse_channel_cfg()
1605 if (chan_cfg->bipolar) in ad4695_parse_channel_cfg()
1606 iio_chan->scan_type.sign = 's'; in ad4695_parse_channel_cfg()
1613 /* Temperature channel must be next scan index after voltage channels. */ in ad4695_parse_channel_cfg()
1614 st->iio_chan[i] = ad4695_temp_channel_template; in ad4695_parse_channel_cfg()
1615 st->iio_chan[i].scan_index = i; in ad4695_parse_channel_cfg()
1618 st->iio_chan[i] = ad4695_soft_timestamp_channel_template; in ad4695_parse_channel_cfg()
1619 st->iio_chan[i].scan_index = i; in ad4695_parse_channel_cfg()
1650 return -EINVAL; in ad4695_offload_trigger_request()
1654 return regmap_set_bits(st->regmap, AD4695_REG_GP_MODE, in ad4695_offload_trigger_request()
1657 return regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE, in ad4695_offload_trigger_request()
1665 if (config->type != SPI_OFFLOAD_TRIGGER_DATA_READY) in ad4695_offload_trigger_validate()
1666 return -EINVAL; in ad4695_offload_trigger_validate()
1689 struct device *dev = &st->spi->dev; in ad4695_probe_spi_offload()
1699 indio_dev->info = &ad4695_offload_info; in ad4695_probe_spi_offload()
1700 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 1; in ad4695_probe_spi_offload()
1701 indio_dev->setup_ops = &ad4695_offload_buffer_setup_ops; in ad4695_probe_spi_offload()
1703 if (!st->cnv_gpio) in ad4695_probe_spi_offload()
1704 return dev_err_probe(dev, -ENODEV, in ad4695_probe_spi_offload()
1712 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, in ad4695_probe_spi_offload()
1714 if (IS_ERR(st->offload_trigger)) in ad4695_probe_spi_offload()
1715 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), in ad4695_probe_spi_offload()
1718 ret = devm_mutex_init(dev, &st->cnv_pwm_lock); in ad4695_probe_spi_offload()
1722 st->cnv_pwm = devm_pwm_get(dev, NULL); in ad4695_probe_spi_offload()
1723 if (IS_ERR(st->cnv_pwm)) in ad4695_probe_spi_offload()
1724 return dev_err_probe(dev, PTR_ERR(st->cnv_pwm), in ad4695_probe_spi_offload()
1727 pwm_init_state(st->cnv_pwm, &pwm_state); in ad4695_probe_spi_offload()
1735 ret = pwm_apply_might_sleep(st->cnv_pwm, &pwm_state); in ad4695_probe_spi_offload()
1739 ret = devm_add_action_or_reset(dev, ad4695_pwm_disable, st->cnv_pwm); in ad4695_probe_spi_offload()
1743 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); in ad4695_probe_spi_offload()
1748 for (i = 0; i < indio_dev->num_channels; i++) { in ad4695_probe_spi_offload()
1749 struct iio_chan_spec *chan = &st->iio_chan[i]; in ad4695_probe_spi_offload()
1761 chan->scan_type.shift = 3; in ad4695_probe_spi_offload()
1762 chan->scan_type.storagebits = 32; in ad4695_probe_spi_offload()
1764 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SAMP_FREQ); in ad4695_probe_spi_offload()
1765 chan->info_mask_separate_available |= BIT(IIO_CHAN_INFO_SAMP_FREQ); in ad4695_probe_spi_offload()
1768 if (chan->type != IIO_VOLTAGE) in ad4695_probe_spi_offload()
1771 cfg = &st->channels_cfg[i]; in ad4695_probe_spi_offload()
1773 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); in ad4695_probe_spi_offload()
1774 chan->info_mask_separate_available |= in ad4695_probe_spi_offload()
1776 chan->has_ext_scan_type = 1; in ad4695_probe_spi_offload()
1777 if (cfg->bipolar) { in ad4695_probe_spi_offload()
1778 chan->ext_scan_type = ad4695_scan_type_offload_s; in ad4695_probe_spi_offload()
1779 chan->num_ext_scan_type = in ad4695_probe_spi_offload()
1782 chan->ext_scan_type = ad4695_scan_type_offload_u; in ad4695_probe_spi_offload()
1783 chan->num_ext_scan_type = in ad4695_probe_spi_offload()
1799 struct device *dev = &spi->dev; in ad4695_probe()
1808 return -ENOMEM; in ad4695_probe()
1811 st->spi = spi; in ad4695_probe()
1813 st->chip_info = spi_get_device_match_data(spi); in ad4695_probe()
1814 if (!st->chip_info) in ad4695_probe()
1815 return -EINVAL; in ad4695_probe()
1817 st->sample_freq_range[0] = 1; /* min */ in ad4695_probe()
1818 st->sample_freq_range[1] = 1; /* step */ in ad4695_probe()
1819 st->sample_freq_range[2] = st->chip_info->max_sample_rate; /* max */ in ad4695_probe()
1821 st->regmap = devm_regmap_init(dev, &ad4695_regmap_bus, st, in ad4695_probe()
1823 if (IS_ERR(st->regmap)) in ad4695_probe()
1824 return dev_err_probe(dev, PTR_ERR(st->regmap), in ad4695_probe()
1827 st->regmap16 = devm_regmap_init(dev, &ad4695_regmap_bus, st, in ad4695_probe()
1829 if (IS_ERR(st->regmap16)) in ad4695_probe()
1830 return dev_err_probe(dev, PTR_ERR(st->regmap16), in ad4695_probe()
1833 st->cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); in ad4695_probe()
1834 if (IS_ERR(st->cnv_gpio)) in ad4695_probe()
1835 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), in ad4695_probe()
1846 ret = devm_regulator_get_enable_optional(dev, "ldo-in"); in ad4695_probe()
1847 if (ret < 0 && ret != -ENODEV) in ad4695_probe()
1863 if (ret < 0 && ret != -ENODEV) in ad4695_probe()
1866 if (ret != -ENODEV) { in ad4695_probe()
1867 st->vref_mv = ret / 1000; in ad4695_probe()
1876 st->vref_mv = ret / 1000; in ad4695_probe()
1881 if (ret < 0 && ret != -ENODEV) in ad4695_probe()
1884 st->com_mv = ret == -ENODEV ? 0 : ret / 1000; in ad4695_probe()
1891 st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); in ad4695_probe()
1892 if (IS_ERR(st->reset_gpio)) in ad4695_probe()
1893 return PTR_ERR(st->reset_gpio); in ad4695_probe()
1895 if (st->reset_gpio) { in ad4695_probe()
1896 gpiod_set_value(st->reset_gpio, 0); in ad4695_probe()
1899 ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A, in ad4695_probe()
1908 ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A, in ad4695_probe()
1914 ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP, in ad4695_probe()
1923 if (device_property_present(dev, "adi,no-ref-current-limit")) { in ad4695_probe()
1924 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, in ad4695_probe()
1930 if (device_property_present(dev, "adi,no-ref-high-z")) { in ad4695_probe()
1932 return dev_err_probe(dev, -EINVAL, in ad4695_probe()
1933 "Cannot disable high-Z mode for internal reference buffer\n"); in ad4695_probe()
1935 ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL, in ad4695_probe()
1941 ret = ad4695_set_ref_voltage(st, st->vref_mv); in ad4695_probe()
1946 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, in ad4695_probe()
1959 indio_dev->name = st->chip_info->name; in ad4695_probe()
1960 indio_dev->info = &ad4695_info; in ad4695_probe()
1961 indio_dev->modes = INDIO_DIRECT_MODE; in ad4695_probe()
1962 indio_dev->channels = st->iio_chan; in ad4695_probe()
1963 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2; in ad4695_probe()
1965 st->offload = devm_spi_offload_get(dev, spi, &ad4695_spi_offload_config); in ad4695_probe()
1966 ret = PTR_ERR_OR_ZERO(st->offload); in ad4695_probe()
1967 if (ret && ret != -ENODEV) in ad4695_probe()
1971 if (ret == -ENODEV) { in ad4695_probe()
1973 if (st->cnv_gpio) in ad4695_probe()
1974 return dev_err_probe(dev, -EINVAL, in ad4695_probe()
1977 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2; in ad4695_probe()