Lines Matching +full:vbias +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
125 #define AD4130_INVALID_SLOT -1
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
393 return -EINVAL; in ad4130_get_reg_size()
427 st->reg_write_tx_buf[0] = reg; in ad4130_reg_write()
431 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
434 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
437 st->reg_write_tx_buf[1] = val; in ad4130_reg_write()
440 return -EINVAL; in ad4130_reg_write()
443 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); in ad4130_reg_write()
451 .tx_buf = st->reg_read_tx_buf, in ad4130_reg_read()
452 .len = sizeof(st->reg_read_tx_buf), in ad4130_reg_read()
455 .rx_buf = st->reg_read_rx_buf, in ad4130_reg_read()
465 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; in ad4130_reg_read()
468 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); in ad4130_reg_read()
474 *val = get_unaligned_be24(st->reg_read_rx_buf); in ad4130_reg_read()
477 *val = get_unaligned_be16(st->reg_read_rx_buf); in ad4130_reg_read()
480 *val = st->reg_read_rx_buf[0]; in ad4130_reg_read()
483 return -EINVAL; in ad4130_reg_read()
502 * Output-only GPIO functionality is available on pins AIN2 through in ad4130_gpio_init_valid_mask()
507 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; in ad4130_gpio_init_valid_mask()
527 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, in ad4130_gpio_set()
533 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mode()
540 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_watermark_interrupt_en()
556 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_mode()
565 unsigned int transfer_len = st->effective_watermark * data_reg_size; in ad4130_push_fifo_data()
566 unsigned int set_size = st->num_enabled_channels * data_reg_size; in ad4130_push_fifo_data()
570 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); in ad4130_push_fifo_data()
571 st->fifo_xfer[1].len = transfer_len; in ad4130_push_fifo_data()
573 ret = spi_sync(st->spi, &st->fifo_msg); in ad4130_push_fifo_data()
578 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); in ad4130_push_fifo_data()
589 complete(&st->completion); in ad4130_irq_handler()
604 struct ad4130_slot_info *slot_info = &st->slots_info[i]; in ad4130_find_slot()
607 if (!memcmp(target_setup_info, &slot_info->setup, in ad4130_find_slot()
614 if (slot_info->enabled_channels) in ad4130_find_slot()
619 slot_info->channels < st->slots_info[*slot].channels) in ad4130_find_slot()
624 return -EINVAL; in ad4130_find_slot()
633 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_unlink_channel()
634 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; in ad4130_unlink_channel()
636 chan_info->slot = AD4130_INVALID_SLOT; in ad4130_unlink_channel()
637 slot_info->channels--; in ad4130_unlink_channel()
645 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_unlink_slot()
647 if (!chan_info->initialized || chan_info->slot != slot) in ad4130_unlink_slot()
659 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; in ad4130_link_channel_slot()
660 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_link_channel_slot()
663 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_link_channel_slot()
669 chan_info->slot = slot; in ad4130_link_channel_slot()
670 slot_info->channels++; in ad4130_link_channel_slot()
682 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) | in ad4130_write_slot_setup()
683 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) | in ad4130_write_slot_setup()
684 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) | in ad4130_write_slot_setup()
685 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) | in ad4130_write_slot_setup()
686 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) | in ad4130_write_slot_setup()
687 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | in ad4130_write_slot_setup()
688 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga); in ad4130_write_slot_setup()
690 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); in ad4130_write_slot_setup()
694 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) | in ad4130_write_slot_setup()
695 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs); in ad4130_write_slot_setup()
697 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); in ad4130_write_slot_setup()
701 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); in ad4130_write_slot_setup()
709 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_write_channel_setup()
710 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_write_channel_setup()
719 * - Find a slot. If not possible, return error. in ad4130_write_channel_setup()
720 * - Unlink channel from current slot. in ad4130_write_channel_setup()
721 * - If the slot has channels linked to it, unlink all channels, and in ad4130_write_channel_setup()
723 * - Link channel to new slot. in ad4130_write_channel_setup()
726 * - Find a slot. If not possible, return error. in ad4130_write_channel_setup()
727 * - If the slot has channels linked to it, unlink all channels, and in ad4130_write_channel_setup()
729 * - Link channel to the slot. in ad4130_write_channel_setup()
732 * - Unlink channel from current slot. in ad4130_write_channel_setup()
736 * - Do nothing. in ad4130_write_channel_setup()
740 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
743 if (!on_enable && !chan_info->enabled) { in ad4130_write_channel_setup()
744 if (chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
757 if (chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
777 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_enable()
781 if (chan_info->enabled == status) in ad4130_set_channel_enable()
790 slot_info = &st->slots_info[chan_info->slot]; in ad4130_set_channel_enable()
792 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_set_channel_enable()
798 slot_info->enabled_channels += status ? 1 : -1; in ad4130_set_channel_enable()
799 chan_info->enabled = status; in ad4130_set_channel_enable()
824 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
825 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
826 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
827 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
832 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
833 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
834 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
846 dividend = filter_config->fs_max * filter_config->odr_div * in ad4130_freq_to_fs()
850 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max - in ad4130_freq_to_fs()
855 else if (temp > filter_config->fs_max) in ad4130_freq_to_fs()
856 temp = filter_config->fs_max; in ad4130_freq_to_fs()
869 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) * in ad4130_fs_to_freq()
871 divisor = filter_config->fs_max * filter_config->odr_div; in ad4130_fs_to_freq()
882 unsigned int channel = chan->scan_index; in ad4130_set_filter_mode()
883 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_filter_mode()
884 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_filter_mode()
890 guard(mutex)(&st->lock); in ad4130_set_filter_mode()
891 if (setup_info->filter_mode == val) in ad4130_set_filter_mode()
894 old_fs = setup_info->fs; in ad4130_set_filter_mode()
895 old_filter_mode = setup_info->filter_mode; in ad4130_set_filter_mode()
903 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, in ad4130_set_filter_mode()
906 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs); in ad4130_set_filter_mode()
908 setup_info->filter_mode = val; in ad4130_set_filter_mode()
912 setup_info->fs = old_fs; in ad4130_set_filter_mode()
913 setup_info->filter_mode = old_filter_mode; in ad4130_set_filter_mode()
924 unsigned int channel = chan->scan_index; in ad4130_get_filter_mode()
925 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_get_filter_mode()
928 guard(mutex)(&st->lock); in ad4130_get_filter_mode()
929 filter_mode = setup_info->filter_mode; in ad4130_get_filter_mode()
968 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_pga()
969 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_channel_pga()
974 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()
975 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()
979 return -EINVAL; in ad4130_set_channel_pga()
981 guard(mutex)(&st->lock); in ad4130_set_channel_pga()
982 if (pga == setup_info->pga) in ad4130_set_channel_pga()
985 old_pga = setup_info->pga; in ad4130_set_channel_pga()
986 setup_info->pga = pga; in ad4130_set_channel_pga()
990 setup_info->pga = old_pga; in ad4130_set_channel_pga()
1000 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_freq()
1001 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_channel_freq()
1005 guard(mutex)(&st->lock); in ad4130_set_channel_freq()
1006 old_fs = setup_info->fs; in ad4130_set_channel_freq()
1008 ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs); in ad4130_set_channel_freq()
1010 if (fs == setup_info->fs) in ad4130_set_channel_freq()
1013 setup_info->fs = fs; in ad4130_set_channel_freq()
1017 setup_info->fs = old_fs; in ad4130_set_channel_freq()
1034 reinit_completion(&st->completion); in _ad4130_read_sample()
1040 ret = wait_for_completion_timeout(&st->completion, in _ad4130_read_sample()
1043 return -ETIMEDOUT; in _ad4130_read_sample()
1049 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); in _ad4130_read_sample()
1063 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { in ad4130_read_sample()
1066 guard(mutex)(&st->lock); in ad4130_read_sample()
1077 unsigned int channel = chan->scan_index; in ad4130_read_raw()
1078 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_raw()
1084 guard(mutex)(&st->lock); in ad4130_read_raw()
1085 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()
1086 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()
1091 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; in ad4130_read_raw()
1095 guard(mutex)(&st->lock); in ad4130_read_raw()
1096 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, in ad4130_read_raw()
1102 return -EINVAL; in ad4130_read_raw()
1112 unsigned int channel = chan->scan_index; in ad4130_read_avail()
1113 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_avail()
1118 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()
1119 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()
1125 scoped_guard(mutex, &st->lock) { in ad4130_read_avail()
1126 filter_config = &ad4130_filter_configs[setup_info->filter_mode]; in ad4130_read_avail()
1129 *vals = (int *)filter_config->samp_freq_avail; in ad4130_read_avail()
1130 *length = filter_config->samp_freq_avail_len * 2; in ad4130_read_avail()
1133 return filter_config->samp_freq_avail_type; in ad4130_read_avail()
1135 return -EINVAL; in ad4130_read_avail()
1148 return -EINVAL; in ad4130_write_raw_get_fmt()
1157 unsigned int channel = chan->scan_index; in ad4130_write_raw()
1165 return -EINVAL; in ad4130_write_raw()
1175 return regmap_read(st->regmap, reg, readval); in ad4130_reg_access()
1177 return regmap_write(st->regmap, reg, writeval); in ad4130_reg_access()
1188 guard(mutex)(&st->lock); in ad4130_update_scan_mode()
1190 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) { in ad4130_update_scan_mode()
1198 st->num_enabled_channels = val; in ad4130_update_scan_mode()
1210 return -EINVAL; in ad4130_set_fifo_watermark()
1212 eff = val * st->num_enabled_channels; in ad4130_set_fifo_watermark()
1218 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); in ad4130_set_fifo_watermark()
1220 guard(mutex)(&st->lock); in ad4130_set_fifo_watermark()
1222 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_watermark()
1229 st->effective_watermark = eff; in ad4130_set_fifo_watermark()
1230 st->watermark = val; in ad4130_set_fifo_watermark()
1250 guard(mutex)(&st->lock); in ad4130_buffer_postenable()
1256 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); in ad4130_buffer_postenable()
1273 guard(mutex)(&st->lock); in ad4130_buffer_predisable()
1279 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); in ad4130_buffer_predisable()
1295 for (i = 0; i < indio_dev->num_channels; i++) { in ad4130_buffer_predisable()
1315 guard(mutex)(&st->lock); in hwfifo_watermark_show()
1316 val = st->watermark; in hwfifo_watermark_show()
1328 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); in hwfifo_enabled_show()
1373 return -EINVAL; in _ad4130_find_table_index()
1384 return regulator_get_voltage(st->regulators[2].consumer); in ad4130_get_ref_voltage()
1386 return regulator_get_voltage(st->regulators[3].consumer); in ad4130_get_ref_voltage()
1388 return regulator_get_voltage(st->regulators[0].consumer); in ad4130_get_ref_voltage()
1390 return st->int_ref_uv; in ad4130_get_ref_voltage()
1392 return -EINVAL; in ad4130_get_ref_voltage()
1400 struct device *dev = &st->spi->dev; in ad4130_parse_fw_setup()
1405 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp); in ad4130_parse_fw_setup()
1410 setup_info->iout0_val = ret; in ad4130_parse_fw_setup()
1413 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp); in ad4130_parse_fw_setup()
1418 setup_info->iout1_val = ret; in ad4130_parse_fw_setup()
1421 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp); in ad4130_parse_fw_setup()
1426 setup_info->burnout = ret; in ad4130_parse_fw_setup()
1428 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive"); in ad4130_parse_fw_setup()
1429 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative"); in ad4130_parse_fw_setup()
1431 setup_info->ref_sel = AD4130_REF_REFIN1; in ad4130_parse_fw_setup()
1432 fwnode_property_read_u32(child, "adi,reference-select", in ad4130_parse_fw_setup()
1433 &setup_info->ref_sel); in ad4130_parse_fw_setup()
1434 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX) in ad4130_parse_fw_setup()
1435 return dev_err_probe(dev, -EINVAL, in ad4130_parse_fw_setup()
1437 setup_info->ref_sel); in ad4130_parse_fw_setup()
1439 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS) in ad4130_parse_fw_setup()
1440 st->int_ref_en = true; in ad4130_parse_fw_setup()
1442 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); in ad4130_parse_fw_setup()
1445 setup_info->ref_sel); in ad4130_parse_fw_setup()
1452 struct device *dev = &st->spi->dev; in ad4130_validate_diff_channel()
1455 return dev_err_probe(dev, -EINVAL, in ad4130_validate_diff_channel()
1461 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_diff_channel()
1462 return dev_err_probe(dev, -EINVAL, in ad4130_validate_diff_channel()
1464 st->pins_fn[pin]); in ad4130_validate_diff_channel()
1466 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; in ad4130_validate_diff_channel()
1488 struct device *dev = &st->spi->dev; in ad4130_validate_excitation_pin()
1491 return dev_err_probe(dev, -EINVAL, in ad4130_validate_excitation_pin()
1494 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_excitation_pin()
1495 return dev_err_probe(dev, -EINVAL, in ad4130_validate_excitation_pin()
1497 st->pins_fn[pin]); in ad4130_validate_excitation_pin()
1499 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; in ad4130_validate_excitation_pin()
1506 struct device *dev = &st->spi->dev; in ad4130_validate_vbias_pin()
1509 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", in ad4130_validate_vbias_pin()
1512 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_vbias_pin()
1513 return dev_err_probe(dev, -EINVAL, in ad4130_validate_vbias_pin()
1515 st->pins_fn[pin]); in ad4130_validate_vbias_pin()
1517 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; in ad4130_validate_vbias_pin()
1528 for (i = 0; i < st->num_vbias_pins; i++) { in ad4130_validate_vbias_pins()
1542 unsigned int index = indio_dev->num_channels++; in ad4130_parse_fw_channel()
1543 struct device *dev = &st->spi->dev; in ad4130_parse_fw_channel()
1550 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); in ad4130_parse_fw_channel()
1552 chan = &st->chans[index]; in ad4130_parse_fw_channel()
1553 chan_info = &st->chans_info[index]; in ad4130_parse_fw_channel()
1556 chan->scan_type.realbits = resolution; in ad4130_parse_fw_channel()
1557 chan->scan_type.storagebits = resolution; in ad4130_parse_fw_channel()
1558 chan->scan_index = index; in ad4130_parse_fw_channel()
1560 chan_info->slot = AD4130_INVALID_SLOT; in ad4130_parse_fw_channel()
1561 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN; in ad4130_parse_fw_channel()
1562 chan_info->initialized = true; in ad4130_parse_fw_channel()
1564 ret = fwnode_property_read_u32_array(child, "diff-channels", pins, in ad4130_parse_fw_channel()
1573 chan->channel = pins[0]; in ad4130_parse_fw_channel()
1574 chan->channel2 = pins[1]; in ad4130_parse_fw_channel()
1576 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); in ad4130_parse_fw_channel()
1580 fwnode_property_read_u32(child, "adi,excitation-pin-0", in ad4130_parse_fw_channel()
1581 &chan_info->iout0); in ad4130_parse_fw_channel()
1582 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) { in ad4130_parse_fw_channel()
1583 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); in ad4130_parse_fw_channel()
1588 fwnode_property_read_u32(child, "adi,excitation-pin-1", in ad4130_parse_fw_channel()
1589 &chan_info->iout1); in ad4130_parse_fw_channel()
1590 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) { in ad4130_parse_fw_channel()
1591 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); in ad4130_parse_fw_channel()
1602 struct device *dev = &st->spi->dev; in ad4130_parse_fw_children()
1605 indio_dev->channels = st->chans; in ad4130_parse_fw_children()
1619 struct device *dev = &st->spi->dev; in ad4310_parse_fw()
1626 st->mclk = devm_clk_get_optional(dev, "mclk"); in ad4310_parse_fw()
1627 if (IS_ERR(st->mclk)) in ad4310_parse_fw()
1628 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad4310_parse_fw()
1631 st->int_pin_sel = AD4130_INT_PIN_INT; in ad4310_parse_fw()
1637 st->int_pin_sel = i; in ad4310_parse_fw()
1642 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) in ad4310_parse_fw()
1643 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1646 if (st->int_pin_sel == AD4130_INT_PIN_P2) in ad4310_parse_fw()
1647 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; in ad4310_parse_fw()
1649 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq); in ad4310_parse_fw()
1652 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1656 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) in ad4310_parse_fw()
1657 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; in ad4310_parse_fw()
1658 else if (st->mclk) in ad4310_parse_fw()
1659 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; in ad4310_parse_fw()
1661 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4310_parse_fw()
1663 if (st->int_pin_sel == AD4130_INT_PIN_CLK && in ad4310_parse_fw()
1664 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4310_parse_fw()
1665 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1667 st->mclk_sel, st->int_pin_sel); in ad4310_parse_fw()
1669 st->int_ref_uv = AD4130_INT_REF_2_5V; in ad4310_parse_fw()
1676 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); in ad4310_parse_fw()
1678 st->int_ref_uv = AD4130_INT_REF_1_25V; in ad4310_parse_fw()
1680 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); in ad4310_parse_fw()
1682 ret = device_property_count_u32(dev, "adi,vbias-pins"); in ad4310_parse_fw()
1685 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1686 "Too many vbias pins %u\n", ret); in ad4310_parse_fw()
1688 st->num_vbias_pins = ret; in ad4310_parse_fw()
1690 ret = device_property_read_u32_array(dev, "adi,vbias-pins", in ad4310_parse_fw()
1691 st->vbias_pins, in ad4310_parse_fw()
1692 st->num_vbias_pins); in ad4310_parse_fw()
1695 "Failed to read vbias pins\n"); in ad4310_parse_fw()
1697 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, in ad4310_parse_fw()
1698 st->num_vbias_pins); in ad4310_parse_fw()
1712 unsigned int pow = ad4130_resolution(st) - st->bipolar; in ad4130_fill_scale_tbls()
1726 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); in ad4130_fill_scale_tbls()
1738 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mclk_sel()
1754 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_is_enabled()
1766 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_prepare()
1780 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4130_int_clk_unprepare()
1792 struct device *dev = &st->spi->dev; in ad4130_setup_int_clk()
1798 if (st->int_pin_sel == AD4130_INT_PIN_CLK || in ad4130_setup_int_clk()
1799 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4130_setup_int_clk()
1805 clk_name = of_node->name; in ad4130_setup_int_clk()
1806 of_property_read_string(of_node, "clock-output-names", &clk_name); in ad4130_setup_int_clk()
1811 st->int_clk_hw.init = &init; in ad4130_setup_int_clk()
1812 ret = devm_clk_hw_register(dev, &st->int_clk_hw); in ad4130_setup_int_clk()
1817 &st->int_clk_hw); in ad4130_setup_int_clk()
1823 struct device *dev = &st->spi->dev; in ad4130_setup()
1830 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) in ad4130_setup()
1833 ret = clk_set_rate(st->mclk, rate); in ad4130_setup()
1837 ret = clk_prepare_enable(st->mclk); in ad4130_setup()
1842 st->mclk); in ad4130_setup()
1846 if (st->int_ref_uv == AD4130_INT_REF_2_5V) in ad4130_setup()
1851 /* Switch to SPI 4-wire mode. */ in ad4130_setup()
1853 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); in ad4130_setup()
1854 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); in ad4130_setup()
1856 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); in ad4130_setup()
1859 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); in ad4130_setup()
1869 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE) in ad4130_setup()
1872 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); in ad4130_setup()
1874 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); in ad4130_setup()
1879 for (i = 0; i < st->num_vbias_pins; i++) in ad4130_setup()
1880 val |= BIT(st->vbias_pins[i]); in ad4130_setup()
1882 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); in ad4130_setup()
1886 ret = regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_setup()
1897 for (i = 0; i < indio_dev->num_channels; i++) { in ad4130_setup()
1898 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_setup()
1899 struct iio_chan_spec *chan = &st->chans[i]; in ad4130_setup()
1902 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) | in ad4130_setup()
1903 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) | in ad4130_setup()
1904 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) | in ad4130_setup()
1905 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1); in ad4130_setup()
1907 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); in ad4130_setup()
1919 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); in ad4130_soft_reset()
1932 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_disable_regulators()
1937 struct device *dev = &spi->dev; in ad4130_probe()
1944 return -ENOMEM; in ad4130_probe()
1948 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); in ad4130_probe()
1949 init_completion(&st->completion); in ad4130_probe()
1950 mutex_init(&st->lock); in ad4130_probe()
1951 st->spi = spi; in ad4130_probe()
1958 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; in ad4130_probe()
1959 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; in ad4130_probe()
1960 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); in ad4130_probe()
1961 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; in ad4130_probe()
1962 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, in ad4130_probe()
1963 ARRAY_SIZE(st->fifo_xfer)); in ad4130_probe()
1965 indio_dev->name = AD4130_NAME; in ad4130_probe()
1966 indio_dev->modes = INDIO_DIRECT_MODE; in ad4130_probe()
1967 indio_dev->info = &ad4130_info; in ad4130_probe()
1969 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); in ad4130_probe()
1970 if (IS_ERR(st->regmap)) in ad4130_probe()
1971 return PTR_ERR(st->regmap); in ad4130_probe()
1973 st->regulators[0].supply = "avdd"; in ad4130_probe()
1974 st->regulators[1].supply = "iovdd"; in ad4130_probe()
1975 st->regulators[2].supply = "refin1"; in ad4130_probe()
1976 st->regulators[3].supply = "refin2"; in ad4130_probe()
1978 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), in ad4130_probe()
1979 st->regulators); in ad4130_probe()
1983 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_probe()
1985 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); in ad4130_probe()
2010 st->gc.owner = THIS_MODULE; in ad4130_probe()
2011 st->gc.label = AD4130_NAME; in ad4130_probe()
2012 st->gc.base = -1; in ad4130_probe()
2013 st->gc.ngpio = AD4130_MAX_GPIOS; in ad4130_probe()
2014 st->gc.parent = dev; in ad4130_probe()
2015 st->gc.can_sleep = true; in ad4130_probe()
2016 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; in ad4130_probe()
2017 st->gc.get_direction = ad4130_gpio_get_direction; in ad4130_probe()
2018 st->gc.set = ad4130_gpio_set; in ad4130_probe()
2020 ret = devm_gpiochip_add_data(dev, &st->gc, st); in ad4130_probe()
2030 ret = devm_request_threaded_irq(dev, spi->irq, NULL, in ad4130_probe()
2032 indio_dev->name, indio_dev); in ad4130_probe()
2044 st->irq_trigger = irq_get_trigger_type(spi->irq); in ad4130_probe()
2045 if (st->irq_trigger & IRQF_TRIGGER_RISING) in ad4130_probe()
2046 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; in ad4130_probe()
2047 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) in ad4130_probe()
2048 st->inv_irq_trigger = IRQF_TRIGGER_RISING; in ad4130_probe()
2050 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", in ad4130_probe()
2051 st->irq_trigger); in ad4130_probe()