47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK	GENMASK(1, 0)
83 #define AD4130_CONFIG_PGA_MASK			GENMASK(3, 1)
88 #define AD4130_FILTER_SELECT_MIN		1
125 #define AD4130_INVALID_SLOT			-1
128 	[AD4130_STATUS_REG] = 1,
133 	[AD4130_ID_REG] = 1,
136 	[AD4130_MCLK_COUNT_REG] = 1,
137 	[AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 	[AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 	[AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 	[AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 	[AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
144 	[AD4130_FIFO_STATUS_REG] = 1,
221 	AD4130_PIN_FN_DIFF = BIT(1),
308 	u8			reg_read_tx_buf[1];
359 		.samp_freq_avail_len = 1,				\
366 	AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4,       1,  10),
368 	AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3,       1,  2047),
369 	AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1,  2047),
389 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg,  in ad4130_get_reg_size()  argument
400 static unsigned int ad4130_data_reg_size(struct ad4130_state *st)  in ad4130_data_reg_size()  argument
405 	ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size);  in ad4130_data_reg_size()
412 static unsigned int ad4130_resolution(struct ad4130_state *st)  in ad4130_resolution()  argument
414 	return ad4130_data_reg_size(st) * BITS_PER_BYTE;  in ad4130_resolution()
419 	struct ad4130_state *st = context;  in ad4130_reg_write()  local
423 	ret = ad4130_get_reg_size(st, reg, &size);  in ad4130_reg_write()
427 	st->reg_write_tx_buf[0] = reg;  in ad4130_reg_write()
431 		put_unaligned_be24(val, &st->reg_write_tx_buf[1]);  in ad4130_reg_write()
434 		put_unaligned_be16(val, &st->reg_write_tx_buf[1]);  in ad4130_reg_write()
436 	case 1:  in ad4130_reg_write()
437 		st->reg_write_tx_buf[1] = val;  in ad4130_reg_write()
443 	return spi_write(st->spi, st->reg_write_tx_buf, size + 1);  in ad4130_reg_write()
448 	struct ad4130_state *st = context;  in ad4130_reg_read()  local
451 			.tx_buf = st->reg_read_tx_buf,  in ad4130_reg_read()
452 			.len = sizeof(st->reg_read_tx_buf),  in ad4130_reg_read()
455 			.rx_buf = st->reg_read_rx_buf,  in ad4130_reg_read()
461 	ret = ad4130_get_reg_size(st, reg, &size);  in ad4130_reg_read()
465 	st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg;  in ad4130_reg_read()
466 	t[1].len = size;  in ad4130_reg_read()
468 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));  in ad4130_reg_read()
474 		*val = get_unaligned_be24(st->reg_read_rx_buf);  in ad4130_reg_read()
477 		*val = get_unaligned_be16(st->reg_read_rx_buf);  in ad4130_reg_read()
479 	case 1:  in ad4130_reg_read()
480 		*val = st->reg_read_rx_buf[0];  in ad4130_reg_read()
498 	struct ad4130_state *st = gpiochip_get_data(gc);  in ad4130_gpio_init_valid_mask()  local
507 		bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE;  in ad4130_gpio_init_valid_mask()
523 	struct ad4130_state *st = gpiochip_get_data(gc);  in ad4130_gpio_set()  local
527 	regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask,  in ad4130_gpio_set()
531 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode)  in ad4130_set_mode()  argument
533 	return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,  in ad4130_set_mode()
538 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en)  in ad4130_set_watermark_interrupt_en()  argument
540 	return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,  in ad4130_set_watermark_interrupt_en()
553 static int ad4130_set_fifo_mode(struct ad4130_state *st,  in ad4130_set_fifo_mode()  argument
556 	return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,  in ad4130_set_fifo_mode()
563 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_push_fifo_data()  local
564 	unsigned int data_reg_size = ad4130_data_reg_size(st);  in ad4130_push_fifo_data()
565 	unsigned int transfer_len = st->effective_watermark * data_reg_size;  in ad4130_push_fifo_data()
566 	unsigned int set_size = st->num_enabled_channels * data_reg_size;  in ad4130_push_fifo_data()
570 	st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark);  in ad4130_push_fifo_data()
571 	st->fifo_xfer[1].len = transfer_len;  in ad4130_push_fifo_data()
573 	ret = spi_sync(st->spi, &st->fifo_msg);  in ad4130_push_fifo_data()
578 		iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]);  in ad4130_push_fifo_data()
584 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_irq_handler()  local
589 		complete(&st->completion);  in ad4130_irq_handler()
594 static int ad4130_find_slot(struct ad4130_state *st,  in ad4130_find_slot()  argument
604 		struct ad4130_slot_info *slot_info = &st->slots_info[i];  in ad4130_find_slot()
619 		    slot_info->channels < st->slots_info[*slot].channels)  in ad4130_find_slot()
631 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel)  in ad4130_unlink_channel()  argument
633 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_unlink_channel()
634 	struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot];  in ad4130_unlink_channel()
640 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot)  in ad4130_unlink_slot()  argument
645 		struct ad4130_chan_info *chan_info = &st->chans_info[i];  in ad4130_unlink_slot()
650 		ad4130_unlink_channel(st, i);  in ad4130_unlink_slot()
656 static int ad4130_link_channel_slot(struct ad4130_state *st,  in ad4130_link_channel_slot()  argument
659 	struct ad4130_slot_info *slot_info = &st->slots_info[slot];  in ad4130_link_channel_slot()
660 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_link_channel_slot()
663 	ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),  in ad4130_link_channel_slot()
675 static int ad4130_write_slot_setup(struct ad4130_state *st,  in ad4130_write_slot_setup()  argument
690 	ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val);  in ad4130_write_slot_setup()
697 	ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val);  in ad4130_write_slot_setup()
701 	memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info));  in ad4130_write_slot_setup()
706 static int ad4130_write_channel_setup(struct ad4130_state *st,  in ad4130_write_channel_setup()  argument
709 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_write_channel_setup()
718 	 * 1. Enabled and linked channel with setup changes:  in ad4130_write_channel_setup()
746 			ad4130_unlink_channel(st, channel);  in ad4130_write_channel_setup()
752 	/* Cases 1 & 2 */  in ad4130_write_channel_setup()
753 	ret = ad4130_find_slot(st, setup_info, &slot, &overwrite);  in ad4130_write_channel_setup()
758 		/* Case 1 */  in ad4130_write_channel_setup()
759 		ad4130_unlink_channel(st, channel);  in ad4130_write_channel_setup()
762 		ret = ad4130_unlink_slot(st, slot);  in ad4130_write_channel_setup()
766 		ret = ad4130_write_slot_setup(st, slot, setup_info);  in ad4130_write_channel_setup()
771 	return ad4130_link_channel_slot(st, channel, slot);  in ad4130_write_channel_setup()
774 static int ad4130_set_channel_enable(struct ad4130_state *st,  in ad4130_set_channel_enable()  argument
777 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_set_channel_enable()
785 		ret = ad4130_write_channel_setup(st, channel, true);  in ad4130_set_channel_enable()
790 	slot_info = &st->slots_info[chan_info->slot];  in ad4130_set_channel_enable()
792 	ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),  in ad4130_set_channel_enable()
798 	slot_info->enabled_channels += status ? 1 : -1;  in ad4130_set_channel_enable()
821  * Notice that FS = 1 actually means max ODR, and that ODR decreases by
824  * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
825  * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
826  * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
827  * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
832  * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
833  * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
834  * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
881 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_set_filter_mode()  local
883 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_set_filter_mode()
890 	guard(mutex)(&st->lock);  in ad4130_set_filter_mode()
910 	ret = ad4130_write_channel_setup(st, channel, false);  in ad4130_set_filter_mode()
923 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_get_filter_mode()  local
925 	struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;  in ad4130_get_filter_mode()
928 	guard(mutex)(&st->lock);  in ad4130_get_filter_mode()
950 	.indexed = 1,
951 	.differential = 1,
965 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel,  in ad4130_set_channel_pga()  argument
968 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_set_channel_pga()
974 		if (val == st->scale_tbls[setup_info->ref_sel][pga][0] &&  in ad4130_set_channel_pga()
975 		    val2 == st->scale_tbls[setup_info->ref_sel][pga][1])  in ad4130_set_channel_pga()
981 	guard(mutex)(&st->lock);  in ad4130_set_channel_pga()
988 	ret = ad4130_write_channel_setup(st, channel, false);  in ad4130_set_channel_pga()
997 static int ad4130_set_channel_freq(struct ad4130_state *st,  in ad4130_set_channel_freq()  argument
1000 	struct ad4130_chan_info *chan_info = &st->chans_info[channel];  in ad4130_set_channel_freq()
1005 	guard(mutex)(&st->lock);  in ad4130_set_channel_freq()
1015 	ret = ad4130_write_channel_setup(st, channel, false);  in ad4130_set_channel_freq()
1027 	struct ad4130_state *st = iio_priv(indio_dev);  in _ad4130_read_sample()  local
1030 	ret = ad4130_set_channel_enable(st, channel, true);  in _ad4130_read_sample()
1034 	reinit_completion(&st->completion);  in _ad4130_read_sample()
1036 	ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);  in _ad4130_read_sample()
1040 	ret = wait_for_completion_timeout(&st->completion,  in _ad4130_read_sample()
1045 	ret = ad4130_set_mode(st, AD4130_MODE_IDLE);  in _ad4130_read_sample()
1049 	ret = regmap_read(st->regmap, AD4130_DATA_REG, val);  in _ad4130_read_sample()
1053 	ret = ad4130_set_channel_enable(st, channel, false);  in _ad4130_read_sample()
1064 		struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_read_sample()  local
1066 		guard(mutex)(&st->lock);  in ad4130_read_sample()
1076 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_read_raw()  local
1078 	struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;  in ad4130_read_raw()
1084 		guard(mutex)(&st->lock);  in ad4130_read_raw()
1085 		*val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0];  in ad4130_read_raw()
1086 		*val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1];  in ad4130_read_raw()
1091 		*val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0;  in ad4130_read_raw()
1095 		guard(mutex)(&st->lock);  in ad4130_read_raw()
1111 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_read_avail()  local
1113 	struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;  in ad4130_read_avail()
1118 		*vals = (int *)st->scale_tbls[setup_info->ref_sel];  in ad4130_read_avail()
1119 		*length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2;  in ad4130_read_avail()
1125 		scoped_guard(mutex, &st->lock) {  in ad4130_read_avail()
1156 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_write_raw()  local
1161 		return ad4130_set_channel_pga(st, channel, val, val2);  in ad4130_write_raw()
1163 		return ad4130_set_channel_freq(st, channel, val, val2);  in ad4130_write_raw()
1172 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_reg_access()  local
1175 		return regmap_read(st->regmap, reg, readval);  in ad4130_reg_access()
1177 	return regmap_write(st->regmap, reg, writeval);  in ad4130_reg_access()
1183 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_update_scan_mode()  local
1188 	guard(mutex)(&st->lock);  in ad4130_update_scan_mode()
1191 		ret = ad4130_set_channel_enable(st, channel, true);  in ad4130_update_scan_mode()
1198 	st->num_enabled_channels = val;  in ad4130_update_scan_mode()
1205 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_set_fifo_watermark()  local
1212 	eff = val * st->num_enabled_channels;  in ad4130_set_fifo_watermark()
1218 		eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels);  in ad4130_set_fifo_watermark()
1220 	guard(mutex)(&st->lock);  in ad4130_set_fifo_watermark()
1222 	ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,  in ad4130_set_fifo_watermark()
1229 	st->effective_watermark = eff;  in ad4130_set_fifo_watermark()
1230 	st->watermark = val;  in ad4130_set_fifo_watermark()
1247 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_buffer_postenable()  local
1250 	guard(mutex)(&st->lock);  in ad4130_buffer_postenable()
1252 	ret = ad4130_set_watermark_interrupt_en(st, true);  in ad4130_buffer_postenable()
1256 	ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger);  in ad4130_buffer_postenable()
1260 	ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM);  in ad4130_buffer_postenable()
1264 	return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);  in ad4130_buffer_postenable()
1269 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_buffer_predisable()  local
1273 	guard(mutex)(&st->lock);  in ad4130_buffer_predisable()
1275 	ret = ad4130_set_mode(st, AD4130_MODE_IDLE);  in ad4130_buffer_predisable()
1279 	ret = irq_set_irq_type(st->spi->irq, st->irq_trigger);  in ad4130_buffer_predisable()
1283 	ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED);  in ad4130_buffer_predisable()
1287 	ret = ad4130_set_watermark_interrupt_en(st, false);  in ad4130_buffer_predisable()
1296 		ret = ad4130_set_channel_enable(st, i, false);  in ad4130_buffer_predisable()
1312 	struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));  in hwfifo_watermark_show()  local
1315 	guard(mutex)(&st->lock);  in hwfifo_watermark_show()
1316 	val = st->watermark;  in hwfifo_watermark_show()
1324 	struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));  in hwfifo_enabled_show()  local
1328 	ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val);  in hwfifo_enabled_show()
1341 	return sysfs_emit(buf, "%s\n", "1");  in hwfifo_watermark_min_show()
1379 static int ad4130_get_ref_voltage(struct ad4130_state *st,  in ad4130_get_ref_voltage()  argument
1384 		return regulator_get_voltage(st->regulators[2].consumer);  in ad4130_get_ref_voltage()
1386 		return regulator_get_voltage(st->regulators[3].consumer);  in ad4130_get_ref_voltage()
1388 		return regulator_get_voltage(st->regulators[0].consumer);  in ad4130_get_ref_voltage()
1390 		return st->int_ref_uv;  in ad4130_get_ref_voltage()
1396 static int ad4130_parse_fw_setup(struct ad4130_state *st,  in ad4130_parse_fw_setup()  argument
1400 	struct device *dev = &st->spi->dev;  in ad4130_parse_fw_setup()
1413 	fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp);  in ad4130_parse_fw_setup()
1440 		st->int_ref_en = true;  in ad4130_parse_fw_setup()
1442 	ret = ad4130_get_ref_voltage(st, setup_info->ref_sel);  in ad4130_parse_fw_setup()
1450 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin)  in ad4130_validate_diff_channel()  argument
1452 	struct device *dev = &st->spi->dev;  in ad4130_validate_diff_channel()
1461 	if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)  in ad4130_validate_diff_channel()
1464 				     st->pins_fn[pin]);  in ad4130_validate_diff_channel()
1466 	st->pins_fn[pin] |= AD4130_PIN_FN_DIFF;  in ad4130_validate_diff_channel()
1471 static int ad4130_validate_diff_channels(struct ad4130_state *st,  in ad4130_validate_diff_channels()  argument
1478 		ret = ad4130_validate_diff_channel(st, pins[i]);  in ad4130_validate_diff_channels()
1486 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin)  in ad4130_validate_excitation_pin()  argument
1488 	struct device *dev = &st->spi->dev;  in ad4130_validate_excitation_pin()
1494 	if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)  in ad4130_validate_excitation_pin()
1497 				     st->pins_fn[pin]);  in ad4130_validate_excitation_pin()
1499 	st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION;  in ad4130_validate_excitation_pin()
1504 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin)  in ad4130_validate_vbias_pin()  argument
1506 	struct device *dev = &st->spi->dev;  in ad4130_validate_vbias_pin()
1512 	if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)  in ad4130_validate_vbias_pin()
1515 				     st->pins_fn[pin]);  in ad4130_validate_vbias_pin()
1517 	st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS;  in ad4130_validate_vbias_pin()
1522 static int ad4130_validate_vbias_pins(struct ad4130_state *st,  in ad4130_validate_vbias_pins()  argument
1528 	for (i = 0; i < st->num_vbias_pins; i++) {  in ad4130_validate_vbias_pins()
1529 		ret = ad4130_validate_vbias_pin(st, pins[i]);  in ad4130_validate_vbias_pins()
1540 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_parse_fw_channel()  local
1541 	unsigned int resolution = ad4130_resolution(st);  in ad4130_parse_fw_channel()
1543 	struct device *dev = &st->spi->dev;  in ad4130_parse_fw_channel()
1552 	chan = &st->chans[index];  in ad4130_parse_fw_channel()
1553 	chan_info = &st->chans_info[index];  in ad4130_parse_fw_channel()
1569 	ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins));  in ad4130_parse_fw_channel()
1574 	chan->channel2 = pins[1];  in ad4130_parse_fw_channel()
1576 	ret = ad4130_parse_fw_setup(st, child, &chan_info->setup);  in ad4130_parse_fw_channel()
1583 		ret = ad4130_validate_excitation_pin(st, chan_info->iout0);  in ad4130_parse_fw_channel()
1588 	fwnode_property_read_u32(child, "adi,excitation-pin-1",  in ad4130_parse_fw_channel()
1591 		ret = ad4130_validate_excitation_pin(st, chan_info->iout1);  in ad4130_parse_fw_channel()
1601 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_parse_fw_children()  local
1602 	struct device *dev = &st->spi->dev;  in ad4130_parse_fw_children()
1605 	indio_dev->channels = st->chans;  in ad4130_parse_fw_children()
1618 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4310_parse_fw()  local
1619 	struct device *dev = &st->spi->dev;  in ad4310_parse_fw()
1626 	st->mclk = devm_clk_get_optional(dev, "mclk");  in ad4310_parse_fw()
1627 	if (IS_ERR(st->mclk))  in ad4310_parse_fw()
1628 		return dev_err_probe(dev, PTR_ERR(st->mclk),  in ad4310_parse_fw()
1631 	st->int_pin_sel = AD4130_INT_PIN_INT;  in ad4310_parse_fw()
1637 			st->int_pin_sel = i;  in ad4310_parse_fw()
1642 	if (st->int_pin_sel == AD4130_INT_PIN_DOUT)  in ad4310_parse_fw()
1646 	if (st->int_pin_sel == AD4130_INT_PIN_P2)  in ad4310_parse_fw()
1647 		st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL;  in ad4310_parse_fw()
1656 	if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ)  in ad4310_parse_fw()
1657 		st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;  in ad4310_parse_fw()
1658 	else if (st->mclk)  in ad4310_parse_fw()
1659 		st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;  in ad4310_parse_fw()
1661 		st->mclk_sel = AD4130_MCLK_76_8KHZ;  in ad4310_parse_fw()
1663 	if (st->int_pin_sel == AD4130_INT_PIN_CLK &&  in ad4310_parse_fw()
1664 	    st->mclk_sel != AD4130_MCLK_76_8KHZ)  in ad4310_parse_fw()
1667 				     st->mclk_sel, st->int_pin_sel);  in ad4310_parse_fw()
1669 	st->int_ref_uv = AD4130_INT_REF_2_5V;  in ad4310_parse_fw()
1676 	avdd_uv = regulator_get_voltage(st->regulators[0].consumer);  in ad4310_parse_fw()
1678 		st->int_ref_uv = AD4130_INT_REF_1_25V;  in ad4310_parse_fw()
1680 	st->bipolar = device_property_read_bool(dev, "adi,bipolar");  in ad4310_parse_fw()
1688 		st->num_vbias_pins = ret;  in ad4310_parse_fw()
1691 						     st->vbias_pins,  in ad4310_parse_fw()
1692 						     st->num_vbias_pins);  in ad4310_parse_fw()
1697 		ret = ad4130_validate_vbias_pins(st, st->vbias_pins,  in ad4310_parse_fw()
1698 						 st->num_vbias_pins);  in ad4310_parse_fw()
1710 static void ad4130_fill_scale_tbls(struct ad4130_state *st)  in ad4130_fill_scale_tbls()  argument
1712 	unsigned int pow = ad4130_resolution(st) - st->bipolar;  in ad4130_fill_scale_tbls()
1719 		ret = ad4130_get_ref_voltage(st, i);  in ad4130_fill_scale_tbls()
1726 			st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI);  in ad4130_fill_scale_tbls()
1735 static int ad4130_set_mclk_sel(struct ad4130_state *st,  in ad4130_set_mclk_sel()  argument
1738 	return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,  in ad4130_set_mclk_sel()
1752 	struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);  in ad4130_int_clk_is_enabled()  local
1754 	return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;  in ad4130_int_clk_is_enabled()
1759 	struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);  in ad4130_int_clk_prepare()  local
1762 	ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT);  in ad4130_int_clk_prepare()
1766 	st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;  in ad4130_int_clk_prepare()
1773 	struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);  in ad4130_int_clk_unprepare()  local
1776 	ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ);  in ad4130_int_clk_unprepare()
1780 	st->mclk_sel = AD4130_MCLK_76_8KHZ;  in ad4130_int_clk_unprepare()
1790 static int ad4130_setup_int_clk(struct ad4130_state *st)  in ad4130_setup_int_clk()  argument
1792 	struct device *dev = &st->spi->dev;  in ad4130_setup_int_clk()
1798 	if (st->int_pin_sel == AD4130_INT_PIN_CLK ||  in ad4130_setup_int_clk()
1799 	    st->mclk_sel != AD4130_MCLK_76_8KHZ)  in ad4130_setup_int_clk()
1811 	st->int_clk_hw.init = &init;  in ad4130_setup_int_clk()
1812 	ret = devm_clk_hw_register(dev, &st->int_clk_hw);  in ad4130_setup_int_clk()
1817 					   &st->int_clk_hw);  in ad4130_setup_int_clk()
1822 	struct ad4130_state *st = iio_priv(indio_dev);  in ad4130_setup()  local
1823 	struct device *dev = &st->spi->dev;  in ad4130_setup()
1830 	if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)  in ad4130_setup()
1833 	ret = clk_set_rate(st->mclk, rate);  in ad4130_setup()
1837 	ret = clk_prepare_enable(st->mclk);  in ad4130_setup()
1842 				       st->mclk);  in ad4130_setup()
1846 	if (st->int_ref_uv == AD4130_INT_REF_2_5V)  in ad4130_setup()
1852 	val =  FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1);  in ad4130_setup()
1853 	val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar);  in ad4130_setup()
1854 	val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en);  in ad4130_setup()
1856 	val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);  in ad4130_setup()
1859 	ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val);  in ad4130_setup()
1869 		if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE)  in ad4130_setup()
1872 	val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel);  in ad4130_setup()
1874 	ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);  in ad4130_setup()
1879 	for (i = 0; i < st->num_vbias_pins; i++)  in ad4130_setup()
1880 		val |= BIT(st->vbias_pins[i]);  in ad4130_setup()
1882 	ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val);  in ad4130_setup()
1886 	ret = regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG,  in ad4130_setup()
1892 	ret = ad4130_set_watermark_interrupt_en(st, false);  in ad4130_setup()
1898 		struct ad4130_chan_info *chan_info = &st->chans_info[i];  in ad4130_setup()
1899 		struct iio_chan_spec *chan = &st->chans[i];  in ad4130_setup()
1907 		ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val);  in ad4130_setup()
1915 static int ad4130_soft_reset(struct ad4130_state *st)  in ad4130_soft_reset()  argument
1919 	ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf));  in ad4130_soft_reset()
1930 	struct ad4130_state *st = data;  in ad4130_disable_regulators()  local
1932 	regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);  in ad4130_disable_regulators()
1939 	struct ad4130_state *st;  in ad4130_probe()  local
1942 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in ad4130_probe()
1946 	st = iio_priv(indio_dev);  in ad4130_probe()
1948 	memset(st->reset_buf, 0xff, sizeof(st->reset_buf));  in ad4130_probe()
1949 	init_completion(&st->completion);  in ad4130_probe()
1950 	mutex_init(&st->lock);  in ad4130_probe()
1951 	st->spi = spi;  in ad4130_probe()
1958 	st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG;  in ad4130_probe()
1959 	st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;  in ad4130_probe()
1960 	st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);  in ad4130_probe()
1961 	st->fifo_xfer[1].rx_buf = st->fifo_rx_buf;  in ad4130_probe()
1962 	spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer,  in ad4130_probe()
1963 					ARRAY_SIZE(st->fifo_xfer));  in ad4130_probe()
1969 	st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config);  in ad4130_probe()
1970 	if (IS_ERR(st->regmap))  in ad4130_probe()
1971 		return PTR_ERR(st->regmap);  in ad4130_probe()
1973 	st->regulators[0].supply = "avdd";  in ad4130_probe()
1974 	st->regulators[1].supply = "iovdd";  in ad4130_probe()
1975 	st->regulators[2].supply = "refin1";  in ad4130_probe()
1976 	st->regulators[3].supply = "refin2";  in ad4130_probe()
1978 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),  in ad4130_probe()
1979 				      st->regulators);  in ad4130_probe()
1983 	ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);  in ad4130_probe()
1987 	ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st);  in ad4130_probe()
1992 	ret = ad4130_soft_reset(st);  in ad4130_probe()
2004 	ret = ad4130_setup_int_clk(st);  in ad4130_probe()
2008 	ad4130_fill_scale_tbls(st);  in ad4130_probe()
2010 	st->gc.owner = THIS_MODULE;  in ad4130_probe()
2011 	st->gc.label = AD4130_NAME;  in ad4130_probe()
2012 	st->gc.base = -1;  in ad4130_probe()
2013 	st->gc.ngpio = AD4130_MAX_GPIOS;  in ad4130_probe()
2014 	st->gc.parent = dev;  in ad4130_probe()
2015 	st->gc.can_sleep = true;  in ad4130_probe()
2016 	st->gc.init_valid_mask = ad4130_gpio_init_valid_mask;  in ad4130_probe()
2017 	st->gc.get_direction = ad4130_gpio_get_direction;  in ad4130_probe()
2018 	st->gc.set = ad4130_gpio_set;  in ad4130_probe()
2020 	ret = devm_gpiochip_add_data(dev, &st->gc, st);  in ad4130_probe()
2044 	st->irq_trigger = irq_get_trigger_type(spi->irq);  in ad4130_probe()
2045 	if (st->irq_trigger & IRQF_TRIGGER_RISING)  in ad4130_probe()
2046 		st->inv_irq_trigger = IRQF_TRIGGER_FALLING;  in ad4130_probe()
2047 	else if (st->irq_trigger & IRQF_TRIGGER_FALLING)  in ad4130_probe()
2048 		st->inv_irq_trigger = IRQF_TRIGGER_RISING;  in ad4130_probe()
2051 				     st->irq_trigger);  in ad4130_probe()