Lines Matching +full:scl +full:- +full:open +full:- +full:drain
1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
162 * struct svc_i3c_master - Silvaco I3C Master structure
170 * @hj_work: Hot-join work
222 * struct svc_i3c_i2c_dev_data - Device specific data
235 return !!(master->enabled_events & mask); in is_events_enabled()
242 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_error()
244 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
245 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
249 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", in svc_i3c_master_error()
254 dev_err(master->dev, in svc_i3c_master_error()
266 writel(mask, master->regs + SVC_I3C_MINTSET); in svc_i3c_master_enable_interrupts()
271 u32 mask = readl(master->regs + SVC_I3C_MINTSET); in svc_i3c_master_disable_interrupts()
273 writel(mask, master->regs + SVC_I3C_MINTCLR); in svc_i3c_master_disable_interrupts()
279 writel(readl(master->regs + SVC_I3C_MERRWARN), in svc_i3c_master_clear_merrwarn()
280 master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_clear_merrwarn()
287 master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_flush_fifo()
300 writel(reg, master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_reset_fifo_trigger()
321 i3c_master_do_daa(&master->base); in svc_i3c_master_hj_work()
331 if (master->addrs[i] == ibiaddr) in svc_i3c_master_dev_from_addr()
337 return master->descs[i]; in svc_i3c_master_dev_from_addr()
342 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_emit_stop()
363 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); in svc_i3c_master_handle_ibi()
365 return -ENOSPC; in svc_i3c_master_handle_ibi()
367 slot->len = 0; in svc_i3c_master_handle_ibi()
368 buf = slot->data; in svc_i3c_master_handle_ibi()
370 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, in svc_i3c_master_handle_ibi()
373 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); in svc_i3c_master_handle_ibi()
377 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && in svc_i3c_master_handle_ibi()
378 slot->len < SVC_I3C_FIFO_SIZE) { in svc_i3c_master_handle_ibi()
379 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_handle_ibi()
381 readsl(master->regs + SVC_I3C_MRDATAB, buf, count); in svc_i3c_master_handle_ibi()
382 slot->len += count; in svc_i3c_master_handle_ibi()
386 master->ibi.tbq_slot = slot; in svc_i3c_master_handle_ibi()
403 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ack_ibi()
405 return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_ack_ibi()
417 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_nack_ibi()
419 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_nack_ibi()
431 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_handle_ibi_won()
453 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5: in svc_i3c_master_ibi_work()
455 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C in svc_i3c_master_ibi_work()
460 guard(spinlock_irqsave)(&master->xferqueue.lock); in svc_i3c_master_ibi_work()
465 * ibitype will be 0 since it was last updated only after the 8th SCL in svc_i3c_master_ibi_work()
473 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
478 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ibi_work()
481 ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val, in svc_i3c_master_ibi_work()
484 dev_err(master->dev, "Timeout when polling for IBIWON\n"); in svc_i3c_master_ibi_work()
489 status = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
521 if (master->ibi.tbq_slot) { in svc_i3c_master_ibi_work()
523 i3c_generic_ibi_recycle_slot(data->ibi_pool, in svc_i3c_master_ibi_work()
524 master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
525 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
537 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
538 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
545 queue_work(master->base.wq, &master->hj_work); in svc_i3c_master_ibi_work()
559 u32 active = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_irq_handler()
565 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_irq_handler()
570 queue_work(master->base.wq, &master->ibi_work); in svc_i3c_master_irq_handler()
579 struct i3c_bus *bus = i3c_master_get_bus(&master->base); in svc_i3c_master_set_speed()
584 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_set_speed()
586 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_set_speed()
592 fclk_rate = clk_get_rate(master->fclk); in svc_i3c_master_set_speed()
594 ret = -EINVAL; in svc_i3c_master_set_speed()
598 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first in svc_i3c_master_set_speed()
603 mconfig = master->mctrl_config; in svc_i3c_master_set_speed()
606 odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1; in svc_i3c_master_set_speed()
609 writel(mconfig, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_set_speed()
612 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_set_speed()
617 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_set_speed()
618 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_set_speed()
634 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_bus_init()
636 dev_err(master->dev, in svc_i3c_master_bus_init()
643 fclk_rate = clk_get_rate(master->fclk); in svc_i3c_master_bus_init()
645 ret = -EINVAL; in svc_i3c_master_bus_init()
650 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c); in svc_i3c_master_bus_init()
651 i2c_scl_rate = bus->scl_rate.i2c; in svc_i3c_master_bus_init()
652 i3c_scl_rate = bus->scl_rate.i3c; in svc_i3c_master_bus_init()
655 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. in svc_i3c_master_bus_init()
656 * Simplest configuration is using a 50% duty-cycle of 40ns. in svc_i3c_master_bus_init()
658 ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1; in svc_i3c_master_bus_init()
662 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a in svc_i3c_master_bus_init()
663 * duty-cycle tuned so that high levels are filetered out by in svc_i3c_master_bus_init()
668 odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2; in svc_i3c_master_bus_init()
671 switch (bus->mode) { in svc_i3c_master_bus_init()
681 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
689 pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud); in svc_i3c_master_bus_init()
694 odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1; in svc_i3c_master_bus_init()
697 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
714 writel(reg, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_init()
716 master->mctrl_config = reg; in svc_i3c_master_bus_init()
725 master->regs + SVC_I3C_MDYNADDR); in svc_i3c_master_bus_init()
727 ret = i3c_master_set_info(&master->base, &info); in svc_i3c_master_bus_init()
732 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_bus_init()
733 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_bus_init()
743 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_bus_cleanup()
745 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_bus_cleanup()
752 writel(0, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_cleanup()
754 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_bus_cleanup()
755 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_bus_cleanup()
762 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) in svc_i3c_master_reserve_slot()
763 return -ENOSPC; in svc_i3c_master_reserve_slot()
765 slot = ffs(master->free_slots) - 1; in svc_i3c_master_reserve_slot()
767 master->free_slots &= ~BIT(slot); in svc_i3c_master_reserve_slot()
775 master->free_slots |= BIT(slot); in svc_i3c_master_release_slot()
792 return -ENOMEM; in svc_i3c_master_attach_i3c_dev()
795 data->ibi = -1; in svc_i3c_master_attach_i3c_dev()
796 data->index = slot; in svc_i3c_master_attach_i3c_dev()
797 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_attach_i3c_dev()
798 dev->info.static_addr; in svc_i3c_master_attach_i3c_dev()
799 master->descs[slot] = dev; in svc_i3c_master_attach_i3c_dev()
813 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_reattach_i3c_dev()
814 dev->info.static_addr; in svc_i3c_master_reattach_i3c_dev()
825 master->addrs[data->index] = 0; in svc_i3c_master_detach_i3c_dev()
826 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i3c_dev()
845 return -ENOMEM; in svc_i3c_master_attach_i2c_dev()
848 data->index = slot; in svc_i3c_master_attach_i2c_dev()
849 master->addrs[slot] = dev->addr; in svc_i3c_master_attach_i2c_dev()
862 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i2c_dev()
874 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_readb()
881 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_readb()
897 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_do_daa_locked()
917 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_do_daa_locked()
923 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_do_daa_locked()
935 * We only care about the 48-bit provisioned ID yet to in svc_i3c_master_do_daa_locked()
944 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); in svc_i3c_master_do_daa_locked()
988 ret = -EIO; in svc_i3c_master_do_daa_locked()
992 dev_nb--; in svc_i3c_master_do_daa_locked()
1003 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_do_daa_locked()
1013 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); in svc_i3c_master_do_daa_locked()
1018 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", in svc_i3c_master_do_daa_locked()
1021 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_do_daa_locked()
1039 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { in svc_i3c_update_ibirules()
1040 if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER) in svc_i3c_update_ibirules()
1043 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { in svc_i3c_update_ibirules()
1045 dev->info.dyn_addr); in svc_i3c_update_ibirules()
1048 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
1054 dev->info.dyn_addr); in svc_i3c_update_ibirules()
1057 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
1073 return -ERANGE; in svc_i3c_update_ibirules()
1077 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
1079 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
1092 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_do_daa()
1094 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_do_daa()
1098 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
1100 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
1128 /* Configure IBI auto-rules */ in svc_i3c_master_do_daa()
1131 dev_err(master->dev, "Cannot handle such a list of devices"); in svc_i3c_master_do_daa()
1134 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_do_daa()
1135 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_do_daa()
1150 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_read()
1155 dev_dbg(master->dev, "I3C read timeout\n"); in svc_i3c_master_read()
1156 return -ETIMEDOUT; in svc_i3c_master_read()
1159 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_read()
1162 dev_err(master->dev, "I3C receive length too long!\n"); in svc_i3c_master_read()
1163 return -EINVAL; in svc_i3c_master_read()
1166 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_read()
1181 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, in svc_i3c_master_write()
1192 if (likely(offset < (len - 1))) in svc_i3c_master_write()
1193 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_write()
1195 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); in svc_i3c_master_write()
1211 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_xfer()
1214 while (retry--) { in svc_i3c_master_xfer()
1221 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_xfer()
1223 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1233 * and so the Controller shall monitor to see whether an In-Band Interrupt request, in svc_i3c_master_xfer()
1235 * Active Controller), or a Hot-Join Request has been made. in svc_i3c_master_xfer()
1248 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) { in svc_i3c_master_xfer()
1250 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3. in svc_i3c_master_xfer()
1270 writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_xfer()
1272 ret = -ENXIO; in svc_i3c_master_xfer()
1291 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1296 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_xfer()
1302 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1324 INIT_LIST_HEAD(&xfer->node); in svc_i3c_master_alloc_xfer()
1325 xfer->ncmds = ncmds; in svc_i3c_master_alloc_xfer()
1326 xfer->ret = -ETIMEDOUT; in svc_i3c_master_alloc_xfer()
1339 if (master->xferqueue.cur == xfer) in svc_i3c_master_dequeue_xfer_locked()
1340 master->xferqueue.cur = NULL; in svc_i3c_master_dequeue_xfer_locked()
1342 list_del_init(&xfer->node); in svc_i3c_master_dequeue_xfer_locked()
1350 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
1352 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
1357 struct svc_i3c_xfer *xfer = master->xferqueue.cur; in svc_i3c_master_start_xfer_locked()
1366 for (i = 0; i < xfer->ncmds; i++) { in svc_i3c_master_start_xfer_locked()
1367 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_start_xfer_locked()
1369 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, in svc_i3c_master_start_xfer_locked()
1370 cmd->addr, cmd->in, cmd->out, in svc_i3c_master_start_xfer_locked()
1371 cmd->len, &cmd->actual_len, in svc_i3c_master_start_xfer_locked()
1372 cmd->continued); in svc_i3c_master_start_xfer_locked()
1373 /* cmd->xfer is NULL if I2C or CCC transfer */ in svc_i3c_master_start_xfer_locked()
1374 if (cmd->xfer) in svc_i3c_master_start_xfer_locked()
1375 cmd->xfer->actual_len = cmd->actual_len; in svc_i3c_master_start_xfer_locked()
1381 xfer->ret = ret; in svc_i3c_master_start_xfer_locked()
1382 complete(&xfer->comp); in svc_i3c_master_start_xfer_locked()
1387 xfer = list_first_entry_or_null(&master->xferqueue.list, in svc_i3c_master_start_xfer_locked()
1391 list_del_init(&xfer->node); in svc_i3c_master_start_xfer_locked()
1393 master->xferqueue.cur = xfer; in svc_i3c_master_start_xfer_locked()
1403 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enqueue_xfer()
1405 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enqueue_xfer()
1409 init_completion(&xfer->comp); in svc_i3c_master_enqueue_xfer()
1410 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1411 if (master->xferqueue.cur) { in svc_i3c_master_enqueue_xfer()
1412 list_add_tail(&xfer->node, &master->xferqueue.list); in svc_i3c_master_enqueue_xfer()
1414 master->xferqueue.cur = xfer; in svc_i3c_master_enqueue_xfer()
1417 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1419 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_enqueue_xfer()
1420 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_enqueue_xfer()
1428 return (cmd->ndests == 1); in svc_i3c_master_supports_ccc_cmd()
1434 unsigned int xfer_len = ccc->dests[0].payload.len + 1; in svc_i3c_master_send_bdcast_ccc_cmd()
1442 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1447 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1450 buf[0] = ccc->id; in svc_i3c_master_send_bdcast_ccc_cmd()
1451 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); in svc_i3c_master_send_bdcast_ccc_cmd()
1453 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_bdcast_ccc_cmd()
1455 cmd = &xfer->cmds[0]; in svc_i3c_master_send_bdcast_ccc_cmd()
1456 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_bdcast_ccc_cmd()
1457 cmd->rnw = ccc->rnw; in svc_i3c_master_send_bdcast_ccc_cmd()
1458 cmd->in = NULL; in svc_i3c_master_send_bdcast_ccc_cmd()
1459 cmd->out = buf; in svc_i3c_master_send_bdcast_ccc_cmd()
1460 cmd->len = xfer_len; in svc_i3c_master_send_bdcast_ccc_cmd()
1461 cmd->actual_len = 0; in svc_i3c_master_send_bdcast_ccc_cmd()
1462 cmd->continued = false; in svc_i3c_master_send_bdcast_ccc_cmd()
1464 mutex_lock(&master->lock); in svc_i3c_master_send_bdcast_ccc_cmd()
1466 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_bdcast_ccc_cmd()
1468 mutex_unlock(&master->lock); in svc_i3c_master_send_bdcast_ccc_cmd()
1470 ret = xfer->ret; in svc_i3c_master_send_bdcast_ccc_cmd()
1480 unsigned int xfer_len = ccc->dests[0].payload.len; in svc_i3c_master_send_direct_ccc_cmd()
1481 unsigned int actual_len = ccc->rnw ? xfer_len : 0; in svc_i3c_master_send_direct_ccc_cmd()
1488 return -ENOMEM; in svc_i3c_master_send_direct_ccc_cmd()
1490 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_direct_ccc_cmd()
1493 cmd = &xfer->cmds[0]; in svc_i3c_master_send_direct_ccc_cmd()
1494 cmd->addr = I3C_BROADCAST_ADDR; in svc_i3c_master_send_direct_ccc_cmd()
1495 cmd->rnw = 0; in svc_i3c_master_send_direct_ccc_cmd()
1496 cmd->in = NULL; in svc_i3c_master_send_direct_ccc_cmd()
1497 cmd->out = &ccc->id; in svc_i3c_master_send_direct_ccc_cmd()
1498 cmd->len = 1; in svc_i3c_master_send_direct_ccc_cmd()
1499 cmd->actual_len = 0; in svc_i3c_master_send_direct_ccc_cmd()
1500 cmd->continued = true; in svc_i3c_master_send_direct_ccc_cmd()
1503 cmd = &xfer->cmds[1]; in svc_i3c_master_send_direct_ccc_cmd()
1504 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_direct_ccc_cmd()
1505 cmd->rnw = ccc->rnw; in svc_i3c_master_send_direct_ccc_cmd()
1506 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; in svc_i3c_master_send_direct_ccc_cmd()
1507 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data; in svc_i3c_master_send_direct_ccc_cmd()
1508 cmd->len = xfer_len; in svc_i3c_master_send_direct_ccc_cmd()
1509 cmd->actual_len = actual_len; in svc_i3c_master_send_direct_ccc_cmd()
1510 cmd->continued = false; in svc_i3c_master_send_direct_ccc_cmd()
1512 mutex_lock(&master->lock); in svc_i3c_master_send_direct_ccc_cmd()
1514 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_direct_ccc_cmd()
1516 mutex_unlock(&master->lock); in svc_i3c_master_send_direct_ccc_cmd()
1518 if (cmd->actual_len != xfer_len) in svc_i3c_master_send_direct_ccc_cmd()
1519 ccc->dests[0].payload.len = cmd->actual_len; in svc_i3c_master_send_direct_ccc_cmd()
1521 ret = xfer->ret; in svc_i3c_master_send_direct_ccc_cmd()
1531 bool broadcast = cmd->id < 0x80; in svc_i3c_master_send_ccc_cmd()
1540 cmd->err = I3C_ERROR_M2; in svc_i3c_master_send_ccc_cmd()
1557 return -ENOMEM; in svc_i3c_master_priv_xfers()
1559 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_priv_xfers()
1562 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_priv_xfers()
1564 cmd->xfer = &xfers[i]; in svc_i3c_master_priv_xfers()
1565 cmd->addr = master->addrs[data->index]; in svc_i3c_master_priv_xfers()
1566 cmd->rnw = xfers[i].rnw; in svc_i3c_master_priv_xfers()
1567 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL; in svc_i3c_master_priv_xfers()
1568 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out; in svc_i3c_master_priv_xfers()
1569 cmd->len = xfers[i].len; in svc_i3c_master_priv_xfers()
1570 cmd->actual_len = xfers[i].rnw ? xfers[i].len : 0; in svc_i3c_master_priv_xfers()
1571 cmd->continued = (i + 1) < nxfers; in svc_i3c_master_priv_xfers()
1574 mutex_lock(&master->lock); in svc_i3c_master_priv_xfers()
1576 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_priv_xfers()
1578 mutex_unlock(&master->lock); in svc_i3c_master_priv_xfers()
1580 ret = xfer->ret; in svc_i3c_master_priv_xfers()
1598 return -ENOMEM; in svc_i3c_master_i2c_xfers()
1600 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; in svc_i3c_master_i2c_xfers()
1603 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_i2c_xfers()
1605 cmd->addr = master->addrs[data->index]; in svc_i3c_master_i2c_xfers()
1606 cmd->rnw = xfers[i].flags & I2C_M_RD; in svc_i3c_master_i2c_xfers()
1607 cmd->in = cmd->rnw ? xfers[i].buf : NULL; in svc_i3c_master_i2c_xfers()
1608 cmd->out = cmd->rnw ? NULL : xfers[i].buf; in svc_i3c_master_i2c_xfers()
1609 cmd->len = xfers[i].len; in svc_i3c_master_i2c_xfers()
1610 cmd->actual_len = cmd->rnw ? xfers[i].len : 0; in svc_i3c_master_i2c_xfers()
1611 cmd->continued = (i + 1 < nxfers); in svc_i3c_master_i2c_xfers()
1614 mutex_lock(&master->lock); in svc_i3c_master_i2c_xfers()
1616 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_i2c_xfers()
1618 mutex_unlock(&master->lock); in svc_i3c_master_i2c_xfers()
1620 ret = xfer->ret; in svc_i3c_master_i2c_xfers()
1635 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { in svc_i3c_master_request_ibi()
1636 dev_err(master->dev, "IBI max payload %d should be < %d\n", in svc_i3c_master_request_ibi()
1637 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); in svc_i3c_master_request_ibi()
1638 return -ERANGE; in svc_i3c_master_request_ibi()
1641 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); in svc_i3c_master_request_ibi()
1642 if (IS_ERR(data->ibi_pool)) in svc_i3c_master_request_ibi()
1643 return PTR_ERR(data->ibi_pool); in svc_i3c_master_request_ibi()
1645 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1646 for (i = 0; i < master->ibi.num_slots; i++) { in svc_i3c_master_request_ibi()
1647 if (!master->ibi.slots[i]) { in svc_i3c_master_request_ibi()
1648 data->ibi = i; in svc_i3c_master_request_ibi()
1649 master->ibi.slots[i] = dev; in svc_i3c_master_request_ibi()
1653 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1655 if (i < master->ibi.num_slots) in svc_i3c_master_request_ibi()
1658 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_request_ibi()
1659 data->ibi_pool = NULL; in svc_i3c_master_request_ibi()
1661 return -ENOSPC; in svc_i3c_master_request_ibi()
1671 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1672 master->ibi.slots[data->ibi] = NULL; in svc_i3c_master_free_ibi()
1673 data->ibi = -1; in svc_i3c_master_free_ibi()
1674 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1676 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_free_ibi()
1685 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enable_ibi()
1687 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enable_ibi()
1691 master->enabled_events++; in svc_i3c_master_enable_ibi()
1694 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_enable_ibi()
1703 master->enabled_events--; in svc_i3c_master_disable_ibi()
1704 if (!master->enabled_events) in svc_i3c_master_disable_ibi()
1707 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_disable_ibi()
1709 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_disable_ibi()
1710 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_disable_ibi()
1720 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enable_hotjoin()
1722 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enable_hotjoin()
1726 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN; in svc_i3c_master_enable_hotjoin()
1737 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN; in svc_i3c_master_disable_hotjoin()
1739 if (!master->enabled_events) in svc_i3c_master_disable_hotjoin()
1742 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_disable_hotjoin()
1743 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_disable_hotjoin()
1753 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); in svc_i3c_master_recycle_ibi_slot()
1783 ret = clk_prepare_enable(master->pclk); in svc_i3c_master_prepare_clks()
1787 ret = clk_prepare_enable(master->fclk); in svc_i3c_master_prepare_clks()
1789 clk_disable_unprepare(master->pclk); in svc_i3c_master_prepare_clks()
1793 ret = clk_prepare_enable(master->sclk); in svc_i3c_master_prepare_clks()
1795 clk_disable_unprepare(master->pclk); in svc_i3c_master_prepare_clks()
1796 clk_disable_unprepare(master->fclk); in svc_i3c_master_prepare_clks()
1805 clk_disable_unprepare(master->pclk); in svc_i3c_master_unprepare_clks()
1806 clk_disable_unprepare(master->fclk); in svc_i3c_master_unprepare_clks()
1807 clk_disable_unprepare(master->sclk); in svc_i3c_master_unprepare_clks()
1812 struct device *dev = &pdev->dev; in svc_i3c_master_probe()
1818 return -ENOMEM; in svc_i3c_master_probe()
1820 master->regs = devm_platform_ioremap_resource(pdev, 0); in svc_i3c_master_probe()
1821 if (IS_ERR(master->regs)) in svc_i3c_master_probe()
1822 return PTR_ERR(master->regs); in svc_i3c_master_probe()
1824 master->pclk = devm_clk_get(dev, "pclk"); in svc_i3c_master_probe()
1825 if (IS_ERR(master->pclk)) in svc_i3c_master_probe()
1826 return PTR_ERR(master->pclk); in svc_i3c_master_probe()
1828 master->fclk = devm_clk_get(dev, "fast_clk"); in svc_i3c_master_probe()
1829 if (IS_ERR(master->fclk)) in svc_i3c_master_probe()
1830 return PTR_ERR(master->fclk); in svc_i3c_master_probe()
1832 master->sclk = devm_clk_get(dev, "slow_clk"); in svc_i3c_master_probe()
1833 if (IS_ERR(master->sclk)) in svc_i3c_master_probe()
1834 return PTR_ERR(master->sclk); in svc_i3c_master_probe()
1836 master->irq = platform_get_irq(pdev, 0); in svc_i3c_master_probe()
1837 if (master->irq < 0) in svc_i3c_master_probe()
1838 return master->irq; in svc_i3c_master_probe()
1840 master->dev = dev; in svc_i3c_master_probe()
1846 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work); in svc_i3c_master_probe()
1847 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work); in svc_i3c_master_probe()
1848 mutex_init(&master->lock); in svc_i3c_master_probe()
1850 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, in svc_i3c_master_probe()
1851 IRQF_NO_SUSPEND, "svc-i3c-irq", master); in svc_i3c_master_probe()
1855 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); in svc_i3c_master_probe()
1857 spin_lock_init(&master->xferqueue.lock); in svc_i3c_master_probe()
1858 INIT_LIST_HEAD(&master->xferqueue.list); in svc_i3c_master_probe()
1860 spin_lock_init(&master->ibi.lock); in svc_i3c_master_probe()
1861 master->ibi.num_slots = SVC_I3C_MAX_DEVS; in svc_i3c_master_probe()
1862 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, in svc_i3c_master_probe()
1863 sizeof(*master->ibi.slots), in svc_i3c_master_probe()
1865 if (!master->ibi.slots) { in svc_i3c_master_probe()
1866 ret = -ENOMEM; in svc_i3c_master_probe()
1872 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); in svc_i3c_master_probe()
1873 pm_runtime_use_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1874 pm_runtime_get_noresume(&pdev->dev); in svc_i3c_master_probe()
1875 pm_runtime_set_active(&pdev->dev); in svc_i3c_master_probe()
1876 pm_runtime_enable(&pdev->dev); in svc_i3c_master_probe()
1881 ret = i3c_master_register(&master->base, &pdev->dev, in svc_i3c_master_probe()
1886 pm_runtime_mark_last_busy(&pdev->dev); in svc_i3c_master_probe()
1887 pm_runtime_put_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1892 pm_runtime_dont_use_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1893 pm_runtime_put_noidle(&pdev->dev); in svc_i3c_master_probe()
1894 pm_runtime_disable(&pdev->dev); in svc_i3c_master_probe()
1895 pm_runtime_set_suspended(&pdev->dev); in svc_i3c_master_probe()
1907 cancel_work_sync(&master->hj_work); in svc_i3c_master_remove()
1908 i3c_master_unregister(&master->base); in svc_i3c_master_remove()
1910 pm_runtime_dont_use_autosuspend(&pdev->dev); in svc_i3c_master_remove()
1911 pm_runtime_disable(&pdev->dev); in svc_i3c_master_remove()
1916 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG); in svc_i3c_save_regs()
1917 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR); in svc_i3c_save_regs()
1922 if (readl(master->regs + SVC_I3C_MDYNADDR) != in svc_i3c_restore_regs()
1923 master->saved_regs.mdynaddr) { in svc_i3c_restore_regs()
1924 writel(master->saved_regs.mconfig, in svc_i3c_restore_regs()
1925 master->regs + SVC_I3C_MCONFIG); in svc_i3c_restore_regs()
1926 writel(master->saved_regs.mdynaddr, in svc_i3c_restore_regs()
1927 master->regs + SVC_I3C_MDYNADDR); in svc_i3c_restore_regs()
1962 { .compatible = "silvaco,i3c-master-v1"},
1971 .name = "silvaco-i3c-master",
1980 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");