Lines Matching +full:i2c +full:- +full:transfer +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
141 * I3C HW stalls the write transfer if the transmit FIFO becomes empty,
142 * when new data is written to FIFO, I3C HW resumes the transfer but
157 * corrupted and results in a no repeated-start condition at the end of
195 * struct svc_i3c_master - Silvaco I3C Master structure
203 * @hj_work: Hot-join work
209 * @xferqueue: Transfer queue structure
211 * @xferqueue.cur: Current ongoing transfer
218 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
257 * struct svc_i3c_i2c_dev_data - Device specific data
270 return (master->drvdata->quirks & quirk);
275 return ((master->drvdata->quirks & SVC_I3C_QUIRK_DAA_CORRUPT) &&
276 !(master->mctrl_config &
282 return !!(master->enabled_events & mask);
289 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
291 merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
292 writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
294 /* Ignore timeout error */
296 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
301 dev_err(master->dev,
313 writel(mask, master->regs + SVC_I3C_MINTSET);
318 u32 mask = readl(master->regs + SVC_I3C_MINTSET);
320 writel(mask, master->regs + SVC_I3C_MINTCLR);
326 writel(readl(master->regs + SVC_I3C_MERRWARN),
327 master->regs + SVC_I3C_MERRWARN);
334 master->regs + SVC_I3C_MDATACTRL);
347 writel(reg, master->regs + SVC_I3C_MDATACTRL);
368 i3c_master_do_daa(&master->base);
378 if (master->addrs[i] == ibiaddr)
384 return master->descs[i];
389 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
410 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
412 return -ENOSPC;
414 slot->len = 0;
415 buf = slot->data;
417 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
420 dev_err(master->dev, "Timeout when polling for COMPLETE\n");
424 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
425 slot->len < SVC_I3C_FIFO_SIZE) {
426 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
428 readsb(master->regs + SVC_I3C_MRDATAB, buf, count);
429 slot->len += count;
433 master->ibi.tbq_slot = slot;
450 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
452 return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
464 master->regs + SVC_I3C_MCTRL);
466 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
478 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
500 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:
502 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C
503 * transfer. But maximum stall time is 100us. The IRQs have to be disabled to prevent
504 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if
507 guard(spinlock_irqsave)(&master->xferqueue.lock);
520 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
525 master->regs + SVC_I3C_MCTRL);
527 /* Wait for IBIWON, should take approximately 100us */
528 ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val,
531 dev_err(master->dev, "Timeout when polling for IBIWON\n");
536 status = readl(master->regs + SVC_I3C_MSTATUS);
568 if (master->ibi.tbq_slot) {
570 i3c_generic_ibi_recycle_slot(data->ibi_pool,
571 master->ibi.tbq_slot);
572 master->ibi.tbq_slot = NULL;
584 i3c_master_queue_ibi(dev, master->ibi.tbq_slot);
585 master->ibi.tbq_slot = NULL;
592 queue_work(master->base.wq, &master->hj_work);
608 u32 active = readl(master->regs + SVC_I3C_MSTATUS);
614 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
624 queue_work(master->base.wq, &master->ibi_work);
633 struct i3c_bus *bus = i3c_master_get_bus(&master->base);
638 ret = pm_runtime_resume_and_get(master->dev);
640 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
646 fclk_rate = clk_get_rate(master->fclk);
648 ret = -EINVAL;
652 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first
653 * broadcast address is visible to all I2C/I3C devices on the I3C bus.
654 * I3C device working as a I2C device will turn off its 50ns Spike
657 mconfig = master->mctrl_config;
660 odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1;
663 writel(mconfig, master->regs + SVC_I3C_MCONFIG);
666 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
671 pm_runtime_mark_last_busy(master->dev);
672 pm_runtime_put_autosuspend(master->dev);
688 ret = pm_runtime_resume_and_get(master->dev);
690 dev_err(master->dev,
697 fclk_rate = clk_get_rate(master->fclk);
699 ret = -EINVAL;
704 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c);
705 i2c_scl_rate = bus->scl_rate.i2c;
706 i3c_scl_rate = bus->scl_rate.i3c;
709 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period.
710 * Simplest configuration is using a 50% duty-cycle of 40ns.
712 ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1;
716 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a
717 * duty-cycle tuned so that high levels are filetered out by
722 odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2;
725 switch (bus->mode) {
732 * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference
735 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2;
740 /* I3C PP + I3C OP + I2C OP both use i2c clk rate */
743 pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud);
748 odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1;
751 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2;
768 writel(reg, master->regs + SVC_I3C_MCONFIG);
770 master->mctrl_config = reg;
779 master->regs + SVC_I3C_MDYNADDR);
781 ret = i3c_master_set_info(&master->base, &info);
786 pm_runtime_mark_last_busy(master->dev);
787 pm_runtime_put_autosuspend(master->dev);
797 ret = pm_runtime_resume_and_get(master->dev);
799 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
806 writel(0, master->regs + SVC_I3C_MCONFIG);
808 pm_runtime_mark_last_busy(master->dev);
809 pm_runtime_put_autosuspend(master->dev);
816 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))
817 return -ENOSPC;
819 slot = ffs(master->free_slots) - 1;
821 master->free_slots &= ~BIT(slot);
829 master->free_slots |= BIT(slot);
846 return -ENOMEM;
849 data->ibi = -1;
850 data->index = slot;
851 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr :
852 dev->info.static_addr;
853 master->descs[slot] = dev;
867 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
868 dev->info.static_addr;
879 master->addrs[data->index] = 0;
880 svc_i3c_master_release_slot(master, data->index);
899 return -ENOMEM;
902 data->index = slot;
903 master->addrs[slot] = dev->addr;
916 svc_i3c_master_release_slot(master, data->index);
928 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
935 dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
953 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
973 master->regs + SVC_I3C_MCTRL);
979 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
1003 ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
1008 writel(dyn_addr, master->regs + SVC_I3C_MWDATAB);
1011 * We only care about the 48-bit provisioned ID yet to
1020 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i));
1064 ret = -EIO;
1068 dev_nb--;
1079 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
1089 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
1110 i3c_bus_for_each_i3cdev(&master->base.bus, dev) {
1111 if (!(dev->info.bcr & I3C_BCR_IBI_REQ_CAP))
1114 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) {
1116 dev->info.dyn_addr);
1119 if (dev->info.dyn_addr & BIT(7))
1125 dev->info.dyn_addr);
1128 if (dev->info.dyn_addr & BIT(7))
1144 return -ERANGE;
1148 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
1150 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
1163 ret = pm_runtime_resume_and_get(master->dev);
1165 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1169 spin_lock_irqsave(&master->xferqueue.lock, flags);
1172 writel(master->mctrl_config | SVC_I3C_MCONFIG_SKEW(1),
1173 master->regs + SVC_I3C_MCONFIG);
1178 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
1180 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1208 /* Configure IBI auto-rules */
1211 dev_err(master->dev, "Cannot handle such a list of devices");
1214 pm_runtime_mark_last_busy(master->dev);
1215 pm_runtime_put_autosuspend(master->dev);
1230 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
1235 dev_dbg(master->dev, "I3C read timeout\n");
1236 return -ETIMEDOUT;
1239 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL);
1242 dev_err(master->dev, "I3C receive length too long!\n");
1243 return -EINVAL;
1246 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
1261 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL,
1272 if (likely(offset < (len - 1)))
1273 writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
1275 writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
1291 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1294 while (retry--) {
1301 master->regs + SVC_I3C_MCTRL);
1306 * immediately, becoming part of the previous transfer.
1314 writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
1316 writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
1317 xfer_len -= len;
1321 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1331 * and so the Controller shall monitor to see whether an In-Band Interrupt request,
1333 * Active Controller), or a Hot-Join Request has been made.
1346 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1348 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.
1368 writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN);
1370 ret = -ENXIO;
1389 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1394 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1400 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1423 INIT_LIST_HEAD(&xfer->node);
1424 xfer->ncmds = ncmds;
1425 xfer->ret = -ETIMEDOUT;
1438 if (master->xferqueue.cur == xfer)
1439 master->xferqueue.cur = NULL;
1441 list_del_init(&xfer->node);
1449 spin_lock_irqsave(&master->xferqueue.lock, flags);
1451 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1456 struct svc_i3c_xfer *xfer = master->xferqueue.cur;
1465 for (i = 0; i < xfer->ncmds; i++) {
1466 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1468 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,
1469 cmd->addr, cmd->in, cmd->out,
1470 cmd->len, &cmd->actual_len,
1471 cmd->continued);
1472 /* cmd->xfer is NULL if I2C or CCC transfer */
1473 if (cmd->xfer)
1474 cmd->xfer->actual_len = cmd->actual_len;
1480 xfer->ret = ret;
1481 complete(&xfer->comp);
1486 xfer = list_first_entry_or_null(&master->xferqueue.list,
1490 list_del_init(&xfer->node);
1492 master->xferqueue.cur = xfer;
1502 ret = pm_runtime_resume_and_get(master->dev);
1504 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1508 init_completion(&xfer->comp);
1509 spin_lock_irqsave(&master->xferqueue.lock, flags);
1510 if (master->xferqueue.cur) {
1511 list_add_tail(&xfer->node, &master->xferqueue.list);
1513 master->xferqueue.cur = xfer;
1516 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1518 pm_runtime_mark_last_busy(master->dev);
1519 pm_runtime_put_autosuspend(master->dev);
1527 return (cmd->ndests == 1);
1533 unsigned int xfer_len = ccc->dests[0].payload.len + 1;
1541 return -ENOMEM;
1546 return -ENOMEM;
1549 buf[0] = ccc->id;
1550 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len);
1552 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1554 cmd = &xfer->cmds[0];
1555 cmd->addr = ccc->dests[0].addr;
1556 cmd->rnw = ccc->rnw;
1557 cmd->in = NULL;
1558 cmd->out = buf;
1559 cmd->len = xfer_len;
1560 cmd->actual_len = 0;
1561 cmd->continued = false;
1563 mutex_lock(&master->lock);
1565 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1567 mutex_unlock(&master->lock);
1569 ret = xfer->ret;
1579 unsigned int xfer_len = ccc->dests[0].payload.len;
1580 unsigned int actual_len = ccc->rnw ? xfer_len : 0;
1587 return -ENOMEM;
1589 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1592 cmd = &xfer->cmds[0];
1593 cmd->addr = I3C_BROADCAST_ADDR;
1594 cmd->rnw = 0;
1595 cmd->in = NULL;
1596 cmd->out = &ccc->id;
1597 cmd->len = 1;
1598 cmd->actual_len = 0;
1599 cmd->continued = true;
1602 cmd = &xfer->cmds[1];
1603 cmd->addr = ccc->dests[0].addr;
1604 cmd->rnw = ccc->rnw;
1605 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL;
1606 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data;
1607 cmd->len = xfer_len;
1608 cmd->actual_len = actual_len;
1609 cmd->continued = false;
1611 mutex_lock(&master->lock);
1613 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1615 mutex_unlock(&master->lock);
1617 if (cmd->actual_len != xfer_len)
1618 ccc->dests[0].payload.len = cmd->actual_len;
1620 ret = xfer->ret;
1630 bool broadcast = cmd->id < 0x80;
1639 cmd->err = I3C_ERROR_M2;
1656 return -ENOMEM;
1658 xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1661 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1663 cmd->xfer = &xfers[i];
1664 cmd->addr = master->addrs[data->index];
1665 cmd->rnw = xfers[i].rnw;
1666 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL;
1667 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out;
1668 cmd->len = xfers[i].len;
1669 cmd->actual_len = xfers[i].rnw ? xfers[i].len : 0;
1670 cmd->continued = (i + 1) < nxfers;
1673 mutex_lock(&master->lock);
1675 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1677 mutex_unlock(&master->lock);
1679 ret = xfer->ret;
1697 return -ENOMEM;
1699 xfer->type = SVC_I3C_MCTRL_TYPE_I2C;
1702 struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1704 cmd->addr = master->addrs[data->index];
1705 cmd->rnw = xfers[i].flags & I2C_M_RD;
1706 cmd->in = cmd->rnw ? xfers[i].buf : NULL;
1707 cmd->out = cmd->rnw ? NULL : xfers[i].buf;
1708 cmd->len = xfers[i].len;
1709 cmd->actual_len = cmd->rnw ? xfers[i].len : 0;
1710 cmd->continued = (i + 1 < nxfers);
1713 mutex_lock(&master->lock);
1715 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1717 mutex_unlock(&master->lock);
1719 ret = xfer->ret;
1734 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) {
1735 dev_err(master->dev, "IBI max payload %d should be < %d\n",
1736 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE);
1737 return -ERANGE;
1740 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1741 if (IS_ERR(data->ibi_pool))
1742 return PTR_ERR(data->ibi_pool);
1744 spin_lock_irqsave(&master->ibi.lock, flags);
1745 for (i = 0; i < master->ibi.num_slots; i++) {
1746 if (!master->ibi.slots[i]) {
1747 data->ibi = i;
1748 master->ibi.slots[i] = dev;
1752 spin_unlock_irqrestore(&master->ibi.lock, flags);
1754 if (i < master->ibi.num_slots)
1757 i3c_generic_ibi_free_pool(data->ibi_pool);
1758 data->ibi_pool = NULL;
1760 return -ENOSPC;
1770 spin_lock_irqsave(&master->ibi.lock, flags);
1771 master->ibi.slots[data->ibi] = NULL;
1772 data->ibi = -1;
1773 spin_unlock_irqrestore(&master->ibi.lock, flags);
1775 i3c_generic_ibi_free_pool(data->ibi_pool);
1784 ret = pm_runtime_resume_and_get(master->dev);
1786 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1790 master->enabled_events++;
1793 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1802 master->enabled_events--;
1803 if (!master->enabled_events)
1806 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1808 pm_runtime_mark_last_busy(master->dev);
1809 pm_runtime_put_autosuspend(master->dev);
1819 ret = pm_runtime_resume_and_get(master->dev);
1821 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1825 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN;
1836 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN;
1838 if (!master->enabled_events)
1841 pm_runtime_mark_last_busy(master->dev);
1842 pm_runtime_put_autosuspend(master->dev);
1852 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1882 ret = clk_prepare_enable(master->pclk);
1886 ret = clk_prepare_enable(master->fclk);
1888 clk_disable_unprepare(master->pclk);
1892 ret = clk_prepare_enable(master->sclk);
1894 clk_disable_unprepare(master->pclk);
1895 clk_disable_unprepare(master->fclk);
1904 clk_disable_unprepare(master->pclk);
1905 clk_disable_unprepare(master->fclk);
1906 clk_disable_unprepare(master->sclk);
1911 struct device *dev = &pdev->dev;
1917 return -ENOMEM;
1919 master->drvdata = of_device_get_match_data(dev);
1920 if (!master->drvdata)
1921 return -EINVAL;
1923 master->regs = devm_platform_ioremap_resource(pdev, 0);
1924 if (IS_ERR(master->regs))
1925 return PTR_ERR(master->regs);
1927 master->pclk = devm_clk_get(dev, "pclk");
1928 if (IS_ERR(master->pclk))
1929 return PTR_ERR(master->pclk);
1931 master->fclk = devm_clk_get(dev, "fast_clk");
1932 if (IS_ERR(master->fclk))
1933 return PTR_ERR(master->fclk);
1935 master->sclk = devm_clk_get(dev, "slow_clk");
1936 if (IS_ERR(master->sclk))
1937 return PTR_ERR(master->sclk);
1939 master->irq = platform_get_irq(pdev, 0);
1940 if (master->irq < 0)
1941 return master->irq;
1943 master->dev = dev;
1949 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);
1950 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);
1951 mutex_init(&master->lock);
1953 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
1954 IRQF_NO_SUSPEND, "svc-i3c-irq", master);
1958 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);
1960 spin_lock_init(&master->xferqueue.lock);
1961 INIT_LIST_HEAD(&master->xferqueue.list);
1963 spin_lock_init(&master->ibi.lock);
1964 master->ibi.num_slots = SVC_I3C_MAX_DEVS;
1965 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1966 sizeof(*master->ibi.slots),
1968 if (!master->ibi.slots) {
1969 ret = -ENOMEM;
1975 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS);
1976 pm_runtime_use_autosuspend(&pdev->dev);
1977 pm_runtime_get_noresume(&pdev->dev);
1978 pm_runtime_set_active(&pdev->dev);
1979 pm_runtime_enable(&pdev->dev);
1984 ret = i3c_master_register(&master->base, &pdev->dev,
1989 pm_runtime_mark_last_busy(&pdev->dev);
1990 pm_runtime_put_autosuspend(&pdev->dev);
1995 pm_runtime_dont_use_autosuspend(&pdev->dev);
1996 pm_runtime_put_noidle(&pdev->dev);
1997 pm_runtime_disable(&pdev->dev);
1998 pm_runtime_set_suspended(&pdev->dev);
2010 cancel_work_sync(&master->hj_work);
2011 i3c_master_unregister(&master->base);
2013 pm_runtime_dont_use_autosuspend(&pdev->dev);
2014 pm_runtime_disable(&pdev->dev);
2019 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG);
2020 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR);
2025 if (readl(master->regs + SVC_I3C_MDYNADDR) !=
2026 master->saved_regs.mdynaddr) {
2027 writel(master->saved_regs.mconfig,
2028 master->regs + SVC_I3C_MCONFIG);
2029 writel(master->saved_regs.mdynaddr,
2030 master->regs + SVC_I3C_MDYNADDR);
2073 { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata },
2074 { .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata },
2083 .name = "silvaco-i3c-master",
2092 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");