3  * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
145  * I3C HW stalls the write transfer if the transmit FIFO becomes empty,
146  * when new data is written to FIFO, I3C HW resumes the transfer but
154  * I3C HW may generate an invalid SlvStart event when emitting a STOP.
203  * struct svc_i3c_master - Silvaco I3C Master structure
204  * @base: I3C master controller
213  * @num_clks: I3C clock number
215  * @clks: I3C clock array
542 	 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:  in svc_i3c_master_ibi_isr()
544 	 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C  in svc_i3c_master_ibi_isr()
546 	 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if  in svc_i3c_master_ibi_isr()
713 		 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first  in svc_i3c_master_set_speed()
714 		 * broadcast address is visible to all I2C/I3C devices on the I3C bus.  in svc_i3c_master_set_speed()
715 		 * I3C device working as a I2C device will turn off its 50ns Spike  in svc_i3c_master_set_speed()
716 		 * Filter to change to I3C mode.  in svc_i3c_master_set_speed()
751 			"<%s> cannot resume i3c bus master, err: %d\n",  in svc_i3c_master_bus_init()
766 	i3c_scl_rate = bus->scl_rate.i3c;  in svc_i3c_master_bus_init()
769 	 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period.  in svc_i3c_master_bus_init()
776 	 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a  in svc_i3c_master_bus_init()
800 		/* I3C PP + I3C OP + I2C OP both use i2c clk rate */  in svc_i3c_master_bus_init()
1105 				/* No I3C devices attached */  in svc_i3c_master_do_daa_locked()
1252 	 * registered on the bus. The I3C stack might still consider 0xb a free  in svc_i3c_master_do_daa()
1254 	 * causing both devices A and B to use the same address 0xb, violating the I3C  in svc_i3c_master_do_daa()
1258 	 * because subsequent steps will scan the entire I3C bus, independent of  in svc_i3c_master_do_daa()
1294 			dev_dbg(master->dev, "I3C read timeout\n");  in svc_i3c_master_read()
1301 			dev_err(master->dev, "I3C receive length too long!\n");  in svc_i3c_master_read()
1402 		 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a  in svc_i3c_master_xfer()
1403 		 * Frame with I3C Target Address.  in svc_i3c_master_xfer()
1405 		 * The I3C Controller normally should start a Frame, the Address may be arbitrated,  in svc_i3c_master_xfer()
1423 			 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.  in svc_i3c_master_xfer()
1424 			 * If the Controller chooses to start an I3C Message with an I3C Dynamic  in svc_i3c_master_xfer()
1425 			 * Address, then special provisions shall be made because that same I3C  in svc_i3c_master_xfer()
2001 		return dev_err_probe(dev, -EINVAL, "can't get I3C clocks\n");  in svc_i3c_master_probe()
2010 				     "can't get I3C peripheral clock\n");  in svc_i3c_master_probe()
2023 		return dev_err_probe(dev, ret, "can't enable I3C clocks\n");  in svc_i3c_master_probe()
2029 			       IRQF_NO_SUSPEND, "svc-i3c-irq", master);  in svc_i3c_master_probe()
2150 	{ .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata },
2151 	{ .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata },
2160 		.name = "silvaco-i3c-master",
2169 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");