Lines Matching full:master
13 #include <linux/i3c/master.h>
26 #include "dw-i3c-master.h"
292 to_dw_i3c_master(struct i3c_master_controller *master) in to_dw_i3c_master() argument
294 return container_of(master, struct dw_i3c_master, base); in to_dw_i3c_master()
297 static void dw_i3c_master_disable(struct dw_i3c_master *master) in dw_i3c_master_disable() argument
299 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, in dw_i3c_master_disable()
300 master->regs + DEVICE_CTRL); in dw_i3c_master_disable()
303 static void dw_i3c_master_enable(struct dw_i3c_master *master) in dw_i3c_master_enable() argument
307 dev_ctrl = readl(master->regs + DEVICE_CTRL); in dw_i3c_master_enable()
310 if (master->i2c_slv_prsnt) in dw_i3c_master_enable()
313 master->regs + DEVICE_CTRL); in dw_i3c_master_enable()
316 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) in dw_i3c_master_get_addr_pos() argument
320 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_get_addr_pos()
321 if (addr == master->devs[pos].addr) in dw_i3c_master_get_addr_pos()
328 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) in dw_i3c_master_get_free_pos() argument
330 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) in dw_i3c_master_get_free_pos()
333 return ffs(master->free_pos) - 1; in dw_i3c_master_get_free_pos()
336 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, in dw_i3c_master_wr_tx_fifo() argument
339 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); in dw_i3c_master_wr_tx_fifo()
344 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1); in dw_i3c_master_wr_tx_fifo()
348 static void dw_i3c_master_read_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_fifo() argument
351 readsl(master->regs + reg, bytes, nbytes / 4); in dw_i3c_master_read_fifo()
355 readsl(master->regs + reg, &tmp, 1); in dw_i3c_master_read_fifo()
360 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_rx_fifo() argument
363 return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes); in dw_i3c_master_read_rx_fifo()
366 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, in dw_i3c_master_read_ibi_fifo() argument
369 return dw_i3c_master_read_fifo(master, IBI_QUEUE_STATUS, bytes, nbytes); in dw_i3c_master_read_ibi_fifo()
373 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) in dw_i3c_master_alloc_xfer() argument
393 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) in dw_i3c_master_start_xfer_locked() argument
395 struct dw_i3c_xfer *xfer = master->xferqueue.cur; in dw_i3c_master_start_xfer_locked()
405 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); in dw_i3c_master_start_xfer_locked()
408 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_start_xfer_locked()
411 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_start_xfer_locked()
416 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); in dw_i3c_master_start_xfer_locked()
417 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); in dw_i3c_master_start_xfer_locked()
421 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, in dw_i3c_master_enqueue_xfer() argument
427 spin_lock_irqsave(&master->xferqueue.lock, flags); in dw_i3c_master_enqueue_xfer()
428 if (master->xferqueue.cur) { in dw_i3c_master_enqueue_xfer()
429 list_add_tail(&xfer->node, &master->xferqueue.list); in dw_i3c_master_enqueue_xfer()
431 master->xferqueue.cur = xfer; in dw_i3c_master_enqueue_xfer()
432 dw_i3c_master_start_xfer_locked(master); in dw_i3c_master_enqueue_xfer()
434 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in dw_i3c_master_enqueue_xfer()
437 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, in dw_i3c_master_dequeue_xfer_locked() argument
440 if (master->xferqueue.cur == xfer) { in dw_i3c_master_dequeue_xfer_locked()
443 master->xferqueue.cur = NULL; in dw_i3c_master_dequeue_xfer_locked()
447 master->regs + RESET_CTRL); in dw_i3c_master_dequeue_xfer_locked()
449 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, in dw_i3c_master_dequeue_xfer_locked()
456 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, in dw_i3c_master_dequeue_xfer() argument
461 spin_lock_irqsave(&master->xferqueue.lock, flags); in dw_i3c_master_dequeue_xfer()
462 dw_i3c_master_dequeue_xfer_locked(master, xfer); in dw_i3c_master_dequeue_xfer()
463 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in dw_i3c_master_dequeue_xfer()
466 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) in dw_i3c_master_end_xfer_locked() argument
468 struct dw_i3c_xfer *xfer = master->xferqueue.cur; in dw_i3c_master_end_xfer_locked()
475 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_master_end_xfer_locked()
482 resp = readl(master->regs + RESPONSE_QUEUE_PORT); in dw_i3c_master_end_xfer_locked()
488 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, in dw_i3c_master_end_xfer_locked()
518 dw_i3c_master_dequeue_xfer_locked(master, xfer); in dw_i3c_master_end_xfer_locked()
519 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, in dw_i3c_master_end_xfer_locked()
520 master->regs + DEVICE_CTRL); in dw_i3c_master_end_xfer_locked()
523 xfer = list_first_entry_or_null(&master->xferqueue.list, in dw_i3c_master_end_xfer_locked()
529 master->xferqueue.cur = xfer; in dw_i3c_master_end_xfer_locked()
530 dw_i3c_master_start_xfer_locked(master); in dw_i3c_master_end_xfer_locked()
533 static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) in dw_i3c_master_set_intr_regs() argument
537 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_set_intr_regs()
543 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); in dw_i3c_master_set_intr_regs()
545 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); in dw_i3c_master_set_intr_regs()
547 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); in dw_i3c_master_set_intr_regs()
549 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_set_intr_regs()
550 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); in dw_i3c_master_set_intr_regs()
551 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); in dw_i3c_master_set_intr_regs()
553 master->sir_rej_mask = IBI_REQ_REJECT_ALL; in dw_i3c_master_set_intr_regs()
554 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); in dw_i3c_master_set_intr_regs()
556 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); in dw_i3c_master_set_intr_regs()
559 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) in dw_i3c_clk_cfg() argument
565 core_rate = clk_get_rate(master->core_clk); in dw_i3c_clk_cfg()
575 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; in dw_i3c_clk_cfg()
580 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); in dw_i3c_clk_cfg()
581 master->i3c_pp_timing = scl_timing; in dw_i3c_clk_cfg()
587 if (master->base.bus.mode == I3C_BUS_MODE_PURE) { in dw_i3c_clk_cfg()
588 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); in dw_i3c_clk_cfg()
589 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); in dw_i3c_clk_cfg()
595 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); in dw_i3c_clk_cfg()
596 master->i3c_od_timing = scl_timing; in dw_i3c_clk_cfg()
606 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); in dw_i3c_clk_cfg()
607 master->ext_lcnt_timing = scl_timing; in dw_i3c_clk_cfg()
612 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) in dw_i2c_clk_cfg() argument
618 core_rate = clk_get_rate(master->core_clk); in dw_i2c_clk_cfg()
628 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); in dw_i2c_clk_cfg()
629 master->i2c_fmp_timing = scl_timing; in dw_i2c_clk_cfg()
635 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); in dw_i2c_clk_cfg()
636 master->i2c_fm_timing = scl_timing; in dw_i2c_clk_cfg()
638 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); in dw_i2c_clk_cfg()
639 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt); in dw_i2c_clk_cfg()
641 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, in dw_i2c_clk_cfg()
642 master->regs + DEVICE_CTRL); in dw_i2c_clk_cfg()
643 master->i2c_slv_prsnt = true; in dw_i2c_clk_cfg()
650 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_bus_init() local
655 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_bus_init()
657 dev_err(master->dev, in dw_i3c_master_bus_init()
658 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_bus_init()
663 ret = master->platform_ops->init(master); in dw_i3c_master_bus_init()
670 ret = dw_i2c_clk_cfg(master); in dw_i3c_master_bus_init()
675 ret = dw_i3c_clk_cfg(master); in dw_i3c_master_bus_init()
689 master->regs + DEVICE_ADDR); in dw_i3c_master_bus_init()
690 master->dev_addr = ret; in dw_i3c_master_bus_init()
694 ret = i3c_master_set_info(&master->base, &info); in dw_i3c_master_bus_init()
698 dw_i3c_master_set_intr_regs(master); in dw_i3c_master_bus_init()
699 dw_i3c_master_enable(master); in dw_i3c_master_bus_init()
702 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_bus_init()
703 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_bus_init()
709 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_bus_cleanup() local
711 dw_i3c_master_disable(master); in dw_i3c_master_bus_cleanup()
714 static int dw_i3c_ccc_set(struct dw_i3c_master *master, in dw_i3c_ccc_set() argument
722 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_set()
727 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_ccc_set()
744 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_ccc_set()
746 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_ccc_set()
757 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) in dw_i3c_ccc_get() argument
763 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_get()
767 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_ccc_get()
785 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_ccc_get()
787 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_ccc_get()
800 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_send_ccc_cmd() local
806 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_send_ccc_cmd()
808 dev_err(master->dev, in dw_i3c_master_send_ccc_cmd()
809 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_send_ccc_cmd()
815 ret = dw_i3c_ccc_get(master, ccc); in dw_i3c_master_send_ccc_cmd()
817 ret = dw_i3c_ccc_set(master, ccc); in dw_i3c_master_send_ccc_cmd()
819 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_send_ccc_cmd()
820 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_send_ccc_cmd()
826 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_daa() local
833 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_daa()
835 dev_err(master->dev, in dw_i3c_master_daa()
836 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_daa()
841 olddevs = ~(master->free_pos); in dw_i3c_master_daa()
844 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_daa()
854 master->devs[pos].addr = ret; in dw_i3c_master_daa()
860 master->regs + in dw_i3c_master_daa()
861 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); in dw_i3c_master_daa()
866 xfer = dw_i3c_master_alloc_xfer(master, 1); in dw_i3c_master_daa()
872 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_daa()
880 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | in dw_i3c_master_daa()
887 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_daa()
889 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_daa()
891 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); in dw_i3c_master_daa()
894 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_daa()
896 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr); in dw_i3c_master_daa()
902 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_daa()
903 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_daa()
913 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_priv_xfers() local
921 if (i3c_nxfers > master->caps.cmdfifodepth) in dw_i3c_master_priv_xfers()
931 if (ntxwords > master->caps.datafifodepth || in dw_i3c_master_priv_xfers()
932 nrxwords > master->caps.datafifodepth) in dw_i3c_master_priv_xfers()
935 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); in dw_i3c_master_priv_xfers()
939 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_priv_xfers()
941 dev_err(master->dev, in dw_i3c_master_priv_xfers()
942 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_priv_xfers()
974 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_priv_xfers()
976 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_priv_xfers()
988 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_priv_xfers()
989 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_priv_xfers()
998 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_reattach_i3c_dev() local
1001 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_reattach_i3c_dev()
1005 master->regs + in dw_i3c_master_reattach_i3c_dev()
1006 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_reattach_i3c_dev()
1008 master->devs[data->index].addr = 0; in dw_i3c_master_reattach_i3c_dev()
1009 master->free_pos |= BIT(data->index); in dw_i3c_master_reattach_i3c_dev()
1012 master->devs[pos].addr = dev->info.dyn_addr; in dw_i3c_master_reattach_i3c_dev()
1013 master->free_pos &= ~BIT(pos); in dw_i3c_master_reattach_i3c_dev()
1017 master->regs + in dw_i3c_master_reattach_i3c_dev()
1018 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_reattach_i3c_dev()
1020 master->devs[data->index].addr = dev->info.dyn_addr; in dw_i3c_master_reattach_i3c_dev()
1028 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_attach_i3c_dev() local
1032 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_attach_i3c_dev()
1041 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr; in dw_i3c_master_attach_i3c_dev()
1042 master->free_pos &= ~BIT(pos); in dw_i3c_master_attach_i3c_dev()
1045 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr), in dw_i3c_master_attach_i3c_dev()
1046 master->regs + in dw_i3c_master_attach_i3c_dev()
1047 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_attach_i3c_dev()
1056 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_detach_i3c_dev() local
1059 master->regs + in dw_i3c_master_detach_i3c_dev()
1060 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_detach_i3c_dev()
1063 master->devs[data->index].addr = 0; in dw_i3c_master_detach_i3c_dev()
1064 master->free_pos |= BIT(data->index); in dw_i3c_master_detach_i3c_dev()
1074 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_i2c_xfers() local
1082 if (i2c_nxfers > master->caps.cmdfifodepth) in dw_i3c_master_i2c_xfers()
1092 if (ntxwords > master->caps.datafifodepth || in dw_i3c_master_i2c_xfers()
1093 nrxwords > master->caps.datafifodepth) in dw_i3c_master_i2c_xfers()
1096 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); in dw_i3c_master_i2c_xfers()
1100 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_i2c_xfers()
1102 dev_err(master->dev, in dw_i3c_master_i2c_xfers()
1103 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_i2c_xfers()
1131 dw_i3c_master_enqueue_xfer(master, xfer); in dw_i3c_master_i2c_xfers()
1133 dw_i3c_master_dequeue_xfer(master, xfer); in dw_i3c_master_i2c_xfers()
1138 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_i2c_xfers()
1139 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_i2c_xfers()
1146 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_attach_i2c_dev() local
1150 pos = dw_i3c_master_get_free_pos(master); in dw_i3c_master_attach_i2c_dev()
1159 master->devs[pos].addr = dev->addr; in dw_i3c_master_attach_i2c_dev()
1160 master->devs[pos].is_i2c_addr = true; in dw_i3c_master_attach_i2c_dev()
1161 master->free_pos &= ~BIT(pos); in dw_i3c_master_attach_i2c_dev()
1166 master->regs + in dw_i3c_master_attach_i2c_dev()
1167 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_attach_i2c_dev()
1176 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_detach_i2c_dev() local
1179 master->regs + in dw_i3c_master_detach_i2c_dev()
1180 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); in dw_i3c_master_detach_i2c_dev()
1183 master->devs[data->index].addr = 0; in dw_i3c_master_detach_i2c_dev()
1184 master->free_pos |= BIT(data->index); in dw_i3c_master_detach_i2c_dev()
1193 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_request_ibi() local
1200 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_request_ibi()
1201 master->devs[data->index].ibi_dev = dev; in dw_i3c_master_request_ibi()
1202 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_request_ibi()
1211 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_free_ibi() local
1214 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_free_ibi()
1215 master->devs[data->index].ibi_dev = NULL; in dw_i3c_master_free_ibi()
1216 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_free_ibi()
1222 static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable) in dw_i3c_master_enable_sir_signal() argument
1226 reg = readl(master->regs + INTR_STATUS_EN); in dw_i3c_master_enable_sir_signal()
1230 writel(reg, master->regs + INTR_STATUS_EN); in dw_i3c_master_enable_sir_signal()
1232 reg = readl(master->regs + INTR_SIGNAL_EN); in dw_i3c_master_enable_sir_signal()
1236 writel(reg, master->regs + INTR_SIGNAL_EN); in dw_i3c_master_enable_sir_signal()
1239 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master, in dw_i3c_master_set_sir_enabled() argument
1247 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx); in dw_i3c_master_set_sir_enabled()
1249 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_set_sir_enabled()
1250 reg = readl(master->regs + dat_entry); in dw_i3c_master_set_sir_enabled()
1258 master->platform_ops->set_dat_ibi(master, dev, enable, ®); in dw_i3c_master_set_sir_enabled()
1259 writel(reg, master->regs + dat_entry); in dw_i3c_master_set_sir_enabled()
1262 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL); in dw_i3c_master_set_sir_enabled()
1263 master->sir_rej_mask &= ~BIT(idx); in dw_i3c_master_set_sir_enabled()
1265 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK); in dw_i3c_master_set_sir_enabled()
1267 master->sir_rej_mask |= BIT(idx); in dw_i3c_master_set_sir_enabled()
1268 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected; in dw_i3c_master_set_sir_enabled()
1270 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); in dw_i3c_master_set_sir_enabled()
1273 dw_i3c_master_enable_sir_signal(master, enable); in dw_i3c_master_set_sir_enabled()
1276 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_set_sir_enabled()
1281 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_enable_hotjoin() local
1284 ret = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_enable_hotjoin()
1286 dev_err(master->dev, in dw_i3c_master_enable_hotjoin()
1287 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_enable_hotjoin()
1292 dw_i3c_master_enable_sir_signal(master, true); in dw_i3c_master_enable_hotjoin()
1293 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK, in dw_i3c_master_enable_hotjoin()
1294 master->regs + DEVICE_CTRL); in dw_i3c_master_enable_hotjoin()
1301 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_disable_hotjoin() local
1303 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, in dw_i3c_master_disable_hotjoin()
1304 master->regs + DEVICE_CTRL); in dw_i3c_master_disable_hotjoin()
1306 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_disable_hotjoin()
1307 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_disable_hotjoin()
1315 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_enable_ibi() local
1318 rc = pm_runtime_resume_and_get(master->dev); in dw_i3c_master_enable_ibi()
1320 dev_err(master->dev, in dw_i3c_master_enable_ibi()
1321 "<%s> cannot resume i3c bus master, err: %d\n", in dw_i3c_master_enable_ibi()
1326 dw_i3c_master_set_sir_enabled(master, dev, data->index, true); in dw_i3c_master_enable_ibi()
1331 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); in dw_i3c_master_enable_ibi()
1332 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_enable_ibi()
1333 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_enable_ibi()
1343 struct dw_i3c_master *master = to_dw_i3c_master(m); in dw_i3c_master_disable_ibi() local
1350 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); in dw_i3c_master_disable_ibi()
1352 pm_runtime_mark_last_busy(master->dev); in dw_i3c_master_disable_ibi()
1353 pm_runtime_put_autosuspend(master->dev); in dw_i3c_master_disable_ibi()
1365 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master, in dw_i3c_master_drain_ibi_queue() argument
1371 readl(master->regs + IBI_QUEUE_STATUS); in dw_i3c_master_drain_ibi_queue()
1374 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master, in dw_i3c_master_handle_ibi_sir() argument
1398 spin_lock_irqsave(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1399 idx = dw_i3c_master_get_addr_pos(master, addr); in dw_i3c_master_handle_ibi_sir()
1401 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1406 dev = master->devs[idx].ibi_dev; in dw_i3c_master_handle_ibi_sir()
1408 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1416 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1422 dev_dbg_ratelimited(&master->base.dev, in dw_i3c_master_handle_ibi_sir()
1429 dw_i3c_master_read_ibi_fifo(master, slot->data, len); in dw_i3c_master_handle_ibi_sir()
1434 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1439 dw_i3c_master_drain_ibi_queue(master, len); in dw_i3c_master_handle_ibi_sir()
1441 spin_unlock_irqrestore(&master->devs_lock, flags); in dw_i3c_master_handle_ibi_sir()
1448 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master) in dw_i3c_master_irq_handle_ibis() argument
1453 reg = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_master_irq_handle_ibis()
1459 reg = readl(master->regs + IBI_QUEUE_STATUS); in dw_i3c_master_irq_handle_ibis()
1462 dw_i3c_master_handle_ibi_sir(master, reg); in dw_i3c_master_irq_handle_ibis()
1464 queue_work(master->base.wq, &master->hj_work); in dw_i3c_master_irq_handle_ibis()
1467 dev_info(&master->base.dev, in dw_i3c_master_irq_handle_ibis()
1470 dw_i3c_master_drain_ibi_queue(master, len); in dw_i3c_master_irq_handle_ibis()
1477 struct dw_i3c_master *master = dev_id; in dw_i3c_master_irq_handler() local
1480 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1482 if (!(status & readl(master->regs + INTR_STATUS_EN))) { in dw_i3c_master_irq_handler()
1483 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1487 spin_lock(&master->xferqueue.lock); in dw_i3c_master_irq_handler()
1488 dw_i3c_master_end_xfer_locked(master, status); in dw_i3c_master_irq_handler()
1490 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1491 spin_unlock(&master->xferqueue.lock); in dw_i3c_master_irq_handler()
1494 dw_i3c_master_irq_handle_ibis(master); in dw_i3c_master_irq_handler()
1540 struct dw_i3c_master *master = in dw_i3c_hj_work() local
1541 container_of(work, typeof(*master), hj_work); in dw_i3c_hj_work()
1543 i3c_master_do_daa(&master->base); in dw_i3c_hj_work()
1546 int dw_i3c_common_probe(struct dw_i3c_master *master, in dw_i3c_common_probe() argument
1551 if (!master->platform_ops) in dw_i3c_common_probe()
1552 master->platform_ops = &dw_i3c_platform_ops_default; in dw_i3c_common_probe()
1554 master->dev = &pdev->dev; in dw_i3c_common_probe()
1556 master->regs = devm_platform_ioremap_resource(pdev, 0); in dw_i3c_common_probe()
1557 if (IS_ERR(master->regs)) in dw_i3c_common_probe()
1558 return PTR_ERR(master->regs); in dw_i3c_common_probe()
1560 master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL); in dw_i3c_common_probe()
1561 if (IS_ERR(master->core_clk)) in dw_i3c_common_probe()
1562 return PTR_ERR(master->core_clk); in dw_i3c_common_probe()
1564 master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk"); in dw_i3c_common_probe()
1565 if (IS_ERR(master->pclk)) in dw_i3c_common_probe()
1566 return PTR_ERR(master->pclk); in dw_i3c_common_probe()
1568 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in dw_i3c_common_probe()
1570 if (IS_ERR(master->core_rst)) in dw_i3c_common_probe()
1571 return PTR_ERR(master->core_rst); in dw_i3c_common_probe()
1573 reset_control_deassert(master->core_rst); in dw_i3c_common_probe()
1575 spin_lock_init(&master->xferqueue.lock); in dw_i3c_common_probe()
1576 INIT_LIST_HEAD(&master->xferqueue.list); in dw_i3c_common_probe()
1578 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_common_probe()
1582 dev_name(&pdev->dev), master); in dw_i3c_common_probe()
1586 platform_set_drvdata(pdev, master); in dw_i3c_common_probe()
1594 ret = readl(master->regs + QUEUE_STATUS_LEVEL); in dw_i3c_common_probe()
1595 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); in dw_i3c_common_probe()
1597 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); in dw_i3c_common_probe()
1598 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); in dw_i3c_common_probe()
1600 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); in dw_i3c_common_probe()
1601 master->datstartaddr = ret; in dw_i3c_common_probe()
1602 master->maxdevs = ret >> 16; in dw_i3c_common_probe()
1603 master->free_pos = GENMASK(master->maxdevs - 1, 0); in dw_i3c_common_probe()
1605 INIT_WORK(&master->hj_work, dw_i3c_hj_work); in dw_i3c_common_probe()
1606 ret = i3c_master_register(&master->base, &pdev->dev, in dw_i3c_common_probe()
1619 reset_control_assert(master->core_rst); in dw_i3c_common_probe()
1625 void dw_i3c_common_remove(struct dw_i3c_master *master) in dw_i3c_common_remove() argument
1627 i3c_master_unregister(&master->base); in dw_i3c_common_remove()
1629 pm_runtime_disable(master->dev); in dw_i3c_common_remove()
1630 pm_runtime_set_suspended(master->dev); in dw_i3c_common_remove()
1631 pm_runtime_dont_use_autosuspend(master->dev); in dw_i3c_common_remove()
1639 struct dw_i3c_master *master; in dw_i3c_probe() local
1641 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); in dw_i3c_probe()
1642 if (!master) in dw_i3c_probe()
1645 return dw_i3c_common_probe(master, pdev); in dw_i3c_probe()
1650 struct dw_i3c_master *master = platform_get_drvdata(pdev); in dw_i3c_remove() local
1652 dw_i3c_common_remove(master); in dw_i3c_remove()
1655 static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master) in dw_i3c_master_restore_addrs() argument
1659 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr), in dw_i3c_master_restore_addrs()
1660 master->regs + DEVICE_ADDR); in dw_i3c_master_restore_addrs()
1662 for (pos = 0; pos < master->maxdevs; pos++) { in dw_i3c_master_restore_addrs()
1663 if (master->free_pos & BIT(pos)) in dw_i3c_master_restore_addrs()
1666 if (master->devs[pos].is_i2c_addr) in dw_i3c_master_restore_addrs()
1668 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr); in dw_i3c_master_restore_addrs()
1670 reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); in dw_i3c_master_restore_addrs()
1672 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); in dw_i3c_master_restore_addrs()
1676 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) in dw_i3c_master_restore_timing_regs() argument
1678 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); in dw_i3c_master_restore_timing_regs()
1679 writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); in dw_i3c_master_restore_timing_regs()
1680 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); in dw_i3c_master_restore_timing_regs()
1681 writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING); in dw_i3c_master_restore_timing_regs()
1683 if (master->i2c_slv_prsnt) { in dw_i3c_master_restore_timing_regs()
1684 writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING); in dw_i3c_master_restore_timing_regs()
1685 writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING); in dw_i3c_master_restore_timing_regs()
1689 static int dw_i3c_master_enable_clks(struct dw_i3c_master *master) in dw_i3c_master_enable_clks() argument
1693 ret = clk_prepare_enable(master->core_clk); in dw_i3c_master_enable_clks()
1697 ret = clk_prepare_enable(master->pclk); in dw_i3c_master_enable_clks()
1699 clk_disable_unprepare(master->core_clk); in dw_i3c_master_enable_clks()
1706 static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master) in dw_i3c_master_disable_clks() argument
1708 clk_disable_unprepare(master->pclk); in dw_i3c_master_disable_clks()
1709 clk_disable_unprepare(master->core_clk); in dw_i3c_master_disable_clks()
1714 struct dw_i3c_master *master = dev_get_drvdata(dev); in dw_i3c_master_runtime_suspend() local
1716 dw_i3c_master_disable(master); in dw_i3c_master_runtime_suspend()
1718 reset_control_assert(master->core_rst); in dw_i3c_master_runtime_suspend()
1719 dw_i3c_master_disable_clks(master); in dw_i3c_master_runtime_suspend()
1726 struct dw_i3c_master *master = dev_get_drvdata(dev); in dw_i3c_master_runtime_resume() local
1729 dw_i3c_master_enable_clks(master); in dw_i3c_master_runtime_resume()
1730 reset_control_deassert(master->core_rst); in dw_i3c_master_runtime_resume()
1732 dw_i3c_master_set_intr_regs(master); in dw_i3c_master_runtime_resume()
1733 dw_i3c_master_restore_timing_regs(master); in dw_i3c_master_runtime_resume()
1734 dw_i3c_master_restore_addrs(master); in dw_i3c_master_runtime_resume()
1736 dw_i3c_master_enable(master); in dw_i3c_master_runtime_resume()
1746 { .compatible = "snps,dw-i3c-master-1.00a", },
1755 .name = "dw-i3c-master",