Lines Matching full:i3c
31 * @bus: I3C bus to take the lock on
42 * logic to rely on I3C device information that could be changed behind their
53 * @bus: I3C bus to release the lock on
66 * @bus: I3C bus to take the lock on
70 * maintenance operations). Basically all communications with I3C devices are
72 * state or I3C dynamic address).
75 * In other words, transfer requests passed to the I3C master can be submitted
76 * in parallel and I3C master drivers have to use their own locking to make
87 * @bus: I3C bus to release the lock on
251 struct i3c_device *i3c = dev_to_i3cdev(dev); in modalias_show() local
255 i3c_device_get_info(i3c, &devinfo); in modalias_show()
261 return sprintf(buf, "i3c:dcr%02Xmanuf%04X", devinfo.dcr, in modalias_show()
264 return sprintf(buf, "i3c:dcr%02Xmanuf%04Xpart%04Xext%04X", in modalias_show()
293 return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X", in i3c_device_uevent()
297 "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04Xext%04X", in i3c_device_uevent()
340 .name = "i3c",
406 * sending it out to the I3C bus. This means that a 7-bit dynamic address needs to be allocated
409 * However, some I3C targets may request specific addresses (called as "init_dyn_addr"), which is
413 * the "init_dyn_addr" to switch to its "init_dyn_addr" when it hot-joins the I3C bus. Otherwise,
414 * if the "init_dyn_addr" is already in use by another I3C device, the target device will not be
474 INIT_LIST_HEAD(&i3cbus->devs.i3c); in i3c_bus_init()
479 id = of_alias_get_id(np, "i3c"); in i3c_bus_init()
582 ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c); in i3c_scl_frequency_show()
650 * @master: I3C master object
662 * @master: I3C master object
709 WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c)); in i3c_masterdev_release()
728 if (!i3cbus->scl_rate.i3c) in i3c_bus_set_mode()
729 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; in i3c_bus_set_mode()
733 if (!i3cbus->scl_rate.i3c) in i3c_bus_set_mode()
734 i3cbus->scl_rate.i3c = I3C_BUS_I3C_SCL_TYP_RATE; in i3c_bus_set_mode()
741 if (!i3cbus->scl_rate.i3c || in i3c_bus_set_mode()
742 i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c) in i3c_bus_set_mode()
743 i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c; in i3c_bus_set_mode()
749 dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n", in i3c_bus_set_mode()
750 i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c); in i3c_bus_set_mode()
753 * I3C/I2C frequency may have been overridden, check that user-provided in i3c_bus_set_mode()
756 if (i3cbus->scl_rate.i3c > I3C_BUS_I3C_SCL_MAX_RATE || in i3c_bus_set_mode()
875 * @master: I3C master object
955 * behind dynamic address assignment has to be handled in the I3C master
960 * Return: 0 in case of success, a positive I3C error code if the error is
1005 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
1013 * Return: 0 in case of success, a positive I3C error code if the error is
1026 * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
1034 * Return: 0 in case of success, a positive I3C error code if the error is
1052 * This should be called after all I3C devices have been discovered (in other
1060 * Return: 0 in case of success, a positive I3C error code if the error is
1117 /* Skip the I3C dev representing this master. */ in i3c_master_defslvs_locked()
1542 list_add_tail(&dev->common.node, &master->bus.devs.i3c); in i3c_master_attach_i3c_dev()
1689 "Failed to add I3C device (err = %d)\n", ret); in i3c_master_register_new_i3c_devs()
1699 * This function is instantiating an I3C device object and adding it to the
1700 * I3C device list. All device information are automatically retrieved using
1703 * The I3C device object is returned in case the master wants to attach
1740 * Return: I3C DMA transfer descriptor or NULL in case of error.
1804 * @info: I3C device information
1866 list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c, in i3c_master_detach_free_devs()
1889 * i3c_master_bus_init() - initialize an I3C bus
1892 * This function is following all initialisation steps described in the I3C
1908 * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices
1910 * the FW with SETDASA and attach corresponding statically defined I3C
1914 * remaining I3C devices
1916 * Once this is done, all I3C and I2C devices should be usable.
2012 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { in i3c_master_bus_init()
2078 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { in i3c_master_attach_boardinfo()
2103 * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus
2105 * @addr: I3C slave dynamic address assigned to the device
2107 * This function is instantiating an I3C device object and adding it to the
2108 * I3C device list. All device information are automatically retrieved using
2111 * The I3C device object is returned in case the master wants to attach
2167 * i3c bus as it does not exist and has been assigned in i3c_master_add_i3c_dev_locked()
2278 * The I3C Specification does not clearly say I2C devices with 10-bit in of_i3c_master_add_i2c_boardinfo()
2339 list_add_tail(&boardinfo->node, &master->boardinfo.i3c); in of_i3c_master_add_i3c_boardinfo()
2389 * The user might want to limit I2C and I3C speed in case some devices in of_populate_i3c_bus()
2396 if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val)) in of_populate_i3c_bus()
2397 master->bus.scl_rate.i3c = val; in of_populate_i3c_bus()
2834 * i3c_master_register() - register an I3C master
2836 * @parent: the parent device (the one that provides this I3C master
2845 * - creates and initializes the I3C bus
2848 * - registers all I3C devices added by the controller during bus
2881 INIT_LIST_HEAD(&master->boardinfo.i3c); in i3c_master_register()
2884 dev_set_name(&master->dev, "i3c-%d", i3cbus->id); in i3c_master_register()
2940 * Expose our I3C bus as an I2C adapter so that I2C devices are exposed in i3c_master_register()
2955 * register I3C devices discovered during the initial DAA. in i3c_master_register()
2978 * i3c_master_unregister() - unregister an I3C master
3133 res = of_alias_get_highest_id("i3c"); in i3c_init()
3166 MODULE_DESCRIPTION("I3C core");