Lines Matching +full:slave +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
14 * This driver is based on i2c-stm32f4.c
21 #include <linux/i2c-smbus.h>
39 #include "i2c-stm32.h"
187 * struct stm32f7_i2c_regs - i2c f7 registers backup
203 * struct stm32f7_i2c_spec - private i2c specification timing
225 * struct stm32f7_i2c_setup - private I2C timing setup parameters
230 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
232 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1
245 * struct stm32f7_i2c_timings - private I2C output parameters
250 * @sclh: SCL high period (master mode)
251 * @scll: SCL low period (master mode)
263 * struct stm32f7_i2c_msg - client specific data
264 * @addr: 8-bit or 10-bit slave addr, including r/w bit
269 * @smbus: boolean to know if the I2C IP is used in SMBus mode
272 * SMBus block read and SMBus block write - block read process call protocols
275 * This buffer has to be 32-bit aligned to be compliant with memory address
276 * register in DMA mode.
291 * struct stm32f7_i2c_alert - SMBus alert specific data
293 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
302 * struct stm32f7_i2c_dev - private data of the controller
315 * @slave: list of slave devices registered on the I2C bus
316 * @slave_running: slave device currently used
318 * @slave_dir: transfer direction for the current slave device
319 * @master_mode: boolean to know in which mode the I2C is running (master or
320 * slave)
323 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
324 * @fmp_sreg: register address for setting Fast Mode Plus bits
325 * @fmp_creg: register address for clearing Fast Mode Plus bits
326 * @fmp_mask: mask for Fast Mode Plus bits in set register
328 * @smbus_mode: states that the controller is configured in SMBus mode
329 * @host_notify_client: SMBus host-notify client
349 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; member
375 * and Fast-mode Plus I2C-bus devices
446 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
457 return ERR_PTR(-EINVAL); in stm32f7_get_specs()
468 setup->clock_src); in stm32f7_i2c_compute_timing()
470 setup->speed_freq); in stm32f7_i2c_compute_timing()
483 specs = stm32f7_get_specs(setup->speed_freq); in stm32f7_i2c_compute_timing()
484 if (specs == ERR_PTR(-EINVAL)) { in stm32f7_i2c_compute_timing()
485 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", in stm32f7_i2c_compute_timing()
486 setup->speed_freq); in stm32f7_i2c_compute_timing()
487 return -EINVAL; in stm32f7_i2c_compute_timing()
490 if ((setup->rise_time > specs->rise_max) || in stm32f7_i2c_compute_timing()
491 (setup->fall_time > specs->fall_max)) { in stm32f7_i2c_compute_timing()
492 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
494 setup->rise_time, specs->rise_max, in stm32f7_i2c_compute_timing()
495 setup->fall_time, specs->fall_max); in stm32f7_i2c_compute_timing()
496 return -EINVAL; in stm32f7_i2c_compute_timing()
499 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); in stm32f7_i2c_compute_timing()
500 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { in stm32f7_i2c_compute_timing()
501 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
503 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); in stm32f7_i2c_compute_timing()
504 return -EINVAL; in stm32f7_i2c_compute_timing()
509 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
512 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
514 dnf_delay = i2c_dev->dnf * i2cclk; in stm32f7_i2c_compute_timing()
516 sdadel_min = specs->hddat_min + setup->fall_time - in stm32f7_i2c_compute_timing()
517 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; in stm32f7_i2c_compute_timing()
519 sdadel_max = specs->vddat_max - setup->rise_time - in stm32f7_i2c_compute_timing()
520 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; in stm32f7_i2c_compute_timing()
522 scldel_min = setup->rise_time + specs->sudat_min; in stm32f7_i2c_compute_timing()
529 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", in stm32f7_i2c_compute_timing()
549 ret = -ENOMEM; in stm32f7_i2c_compute_timing()
553 v->presc = p; in stm32f7_i2c_compute_timing()
554 v->scldel = l; in stm32f7_i2c_compute_timing()
555 v->sdadel = a; in stm32f7_i2c_compute_timing()
558 list_add_tail(&v->node, in stm32f7_i2c_compute_timing()
570 dev_err(i2c_dev->dev, "no Prescaler solution\n"); in stm32f7_i2c_compute_timing()
571 ret = -EPERM; in stm32f7_i2c_compute_timing()
577 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); in stm32f7_i2c_compute_timing()
578 clk_min = NSEC_PER_SEC / setup->speed_freq; in stm32f7_i2c_compute_timing()
583 * - SCL Low Period has to be higher than SCL Clock Low Period in stm32f7_i2c_compute_timing()
585 * (SCL Low Period - Analog/Digital filters) / 4. in stm32f7_i2c_compute_timing()
586 * - SCL High Period has to be lower than SCL Clock High Period in stm32f7_i2c_compute_timing()
588 * - I2C Clock has to be lower than SCL High Period in stm32f7_i2c_compute_timing()
591 u32 prescaler = (v->presc + 1) * i2cclk; in stm32f7_i2c_compute_timing()
596 if ((tscl_l < specs->l_min) || in stm32f7_i2c_compute_timing()
598 ((tscl_l - af_delay_min - dnf_delay) / 4))) { in stm32f7_i2c_compute_timing()
605 setup->rise_time + setup->fall_time; in stm32f7_i2c_compute_timing()
608 (tscl_h >= specs->h_min) && in stm32f7_i2c_compute_timing()
610 int clk_error = tscl - i2cbus; in stm32f7_i2c_compute_timing()
613 clk_error = -clk_error; in stm32f7_i2c_compute_timing()
617 v->scll = l; in stm32f7_i2c_compute_timing()
618 v->sclh = h; in stm32f7_i2c_compute_timing()
627 dev_err(i2c_dev->dev, "no solution at all\n"); in stm32f7_i2c_compute_timing()
628 ret = -EPERM; in stm32f7_i2c_compute_timing()
632 output->presc = s->presc; in stm32f7_i2c_compute_timing()
633 output->scldel = s->scldel; in stm32f7_i2c_compute_timing()
634 output->sdadel = s->sdadel; in stm32f7_i2c_compute_timing()
635 output->scll = s->scll; in stm32f7_i2c_compute_timing()
636 output->sclh = s->sclh; in stm32f7_i2c_compute_timing()
638 dev_dbg(i2c_dev->dev, in stm32f7_i2c_compute_timing()
640 output->presc, in stm32f7_i2c_compute_timing()
641 output->scldel, output->sdadel, in stm32f7_i2c_compute_timing()
642 output->scll, output->sclh); in stm32f7_i2c_compute_timing()
647 list_del(&v->node); in stm32f7_i2c_compute_timing()
658 while (--i) in stm32f7_get_lower_rate()
671 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in stm32f7_i2c_setup_timing()
672 t->scl_rise_ns = i2c_dev->setup.rise_time; in stm32f7_i2c_setup_timing()
673 t->scl_fall_ns = i2c_dev->setup.fall_time; in stm32f7_i2c_setup_timing()
675 i2c_parse_fw_timings(i2c_dev->dev, t, false); in stm32f7_i2c_setup_timing()
677 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { in stm32f7_i2c_setup_timing()
678 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", in stm32f7_i2c_setup_timing()
679 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); in stm32f7_i2c_setup_timing()
680 return -EINVAL; in stm32f7_i2c_setup_timing()
683 setup->speed_freq = t->bus_freq_hz; in stm32f7_i2c_setup_timing()
684 i2c_dev->setup.rise_time = t->scl_rise_ns; in stm32f7_i2c_setup_timing()
685 i2c_dev->setup.fall_time = t->scl_fall_ns; in stm32f7_i2c_setup_timing()
686 i2c_dev->dnf_dt = t->digital_filter_width_ns; in stm32f7_i2c_setup_timing()
687 setup->clock_src = clk_get_rate(i2c_dev->clk); in stm32f7_i2c_setup_timing()
689 if (!setup->clock_src) { in stm32f7_i2c_setup_timing()
690 dev_err(i2c_dev->dev, "clock rate is 0\n"); in stm32f7_i2c_setup_timing()
691 return -EINVAL; in stm32f7_i2c_setup_timing()
694 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) in stm32f7_i2c_setup_timing()
695 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; in stm32f7_i2c_setup_timing()
699 &i2c_dev->timing); in stm32f7_i2c_setup_timing()
701 dev_err(i2c_dev->dev, in stm32f7_i2c_setup_timing()
703 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) in stm32f7_i2c_setup_timing()
705 setup->speed_freq = in stm32f7_i2c_setup_timing()
706 stm32f7_get_lower_rate(setup->speed_freq); in stm32f7_i2c_setup_timing()
707 dev_warn(i2c_dev->dev, in stm32f7_i2c_setup_timing()
709 setup->speed_freq); in stm32f7_i2c_setup_timing()
714 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
718 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, in stm32f7_i2c_setup_timing()
719 "i2c-analog-filter"); in stm32f7_i2c_setup_timing()
721 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", in stm32f7_i2c_setup_timing()
722 setup->speed_freq, setup->clock_src); in stm32f7_i2c_setup_timing()
723 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", in stm32f7_i2c_setup_timing()
724 setup->rise_time, setup->fall_time); in stm32f7_i2c_setup_timing()
725 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", in stm32f7_i2c_setup_timing()
726 str_on_off(i2c_dev->analog_filter), i2c_dev->dnf); in stm32f7_i2c_setup_timing()
728 i2c_dev->bus_rate = setup->speed_freq; in stm32f7_i2c_setup_timing()
735 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_dma_req()
744 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_dma_callback()
745 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_dma_callback()
748 dmaengine_terminate_async(dma->chan_using); in stm32f7_i2c_dma_callback()
749 dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len, in stm32f7_i2c_dma_callback()
750 dma->dma_data_dir); in stm32f7_i2c_dma_callback()
751 if (!f7_msg->smbus) in stm32f7_i2c_dma_callback()
752 i2c_put_dma_safe_msg_buf(f7_msg->buf, i2c_dev->msg, true); in stm32f7_i2c_dma_callback()
753 complete(&dma->dma_complete); in stm32f7_i2c_dma_callback()
758 struct stm32f7_i2c_timings *t = &i2c_dev->timing; in stm32f7_i2c_hw_config()
762 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); in stm32f7_i2c_hw_config()
763 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); in stm32f7_i2c_hw_config()
764 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); in stm32f7_i2c_hw_config()
765 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); in stm32f7_i2c_hw_config()
766 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); in stm32f7_i2c_hw_config()
767 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_hw_config()
770 if (i2c_dev->analog_filter) in stm32f7_i2c_hw_config()
771 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
774 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
778 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
780 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
781 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); in stm32f7_i2c_hw_config()
783 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_write_tx_data()
790 void __iomem *base = i2c_dev->base; in stm32f7_i2c_write_tx_data()
792 if (f7_msg->count) { in stm32f7_i2c_write_tx_data()
793 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); in stm32f7_i2c_write_tx_data()
794 f7_msg->count--; in stm32f7_i2c_write_tx_data()
800 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_read_rx_data()
801 void __iomem *base = i2c_dev->base; in stm32f7_i2c_read_rx_data()
803 if (f7_msg->count) { in stm32f7_i2c_read_rx_data()
804 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); in stm32f7_i2c_read_rx_data()
805 f7_msg->count--; in stm32f7_i2c_read_rx_data()
814 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_reload()
817 if (i2c_dev->use_dma) in stm32f7_i2c_reload()
818 f7_msg->count -= STM32F7_I2C_MAX_LEN; in stm32f7_i2c_reload()
820 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
823 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_reload()
827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_reload()
830 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
835 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_reload()
848 val = f7_msg->buf - sizeof(u8); in stm32f7_i2c_smbus_reload()
849 f7_msg->count = *val; in stm32f7_i2c_smbus_reload()
850 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
852 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_reload()
853 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
860 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
871 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, in stm32f7_i2c_wait_free_bus()
878 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_wait_free_bus()
880 return -EBUSY; in stm32f7_i2c_wait_free_bus()
886 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer_msg()
887 void __iomem *base = i2c_dev->base; in stm32f7_i2c_xfer_msg()
892 f7_msg->addr = msg->addr; in stm32f7_i2c_xfer_msg()
893 f7_msg->buf = msg->buf; in stm32f7_i2c_xfer_msg()
894 f7_msg->count = msg->len; in stm32f7_i2c_xfer_msg()
895 f7_msg->result = 0; in stm32f7_i2c_xfer_msg()
896 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); in stm32f7_i2c_xfer_msg()
898 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_xfer_msg()
905 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
908 /* Set slave address */ in stm32f7_i2c_xfer_msg()
910 if (msg->flags & I2C_M_TEN) { in stm32f7_i2c_xfer_msg()
912 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); in stm32f7_i2c_xfer_msg()
916 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_xfer_msg()
921 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_xfer_msg()
925 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_xfer_msg()
937 i2c_dev->use_dma = false; in stm32f7_i2c_xfer_msg()
938 if (i2c_dev->dma && !i2c_dev->atomic) { in stm32f7_i2c_xfer_msg()
941 f7_msg->buf = dma_buf; in stm32f7_i2c_xfer_msg()
942 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_xfer_msg()
943 msg->flags & I2C_M_RD, in stm32f7_i2c_xfer_msg()
944 f7_msg->count, f7_msg->buf, in stm32f7_i2c_xfer_msg()
948 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_xfer_msg()
949 i2c_put_dma_safe_msg_buf(f7_msg->buf, msg, false); in stm32f7_i2c_xfer_msg()
950 f7_msg->buf = msg->buf; in stm32f7_i2c_xfer_msg()
952 i2c_dev->use_dma = true; in stm32f7_i2c_xfer_msg()
957 if (!i2c_dev->use_dma) { in stm32f7_i2c_xfer_msg()
958 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
963 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
969 if (i2c_dev->atomic) in stm32f7_i2c_xfer_msg()
975 i2c_dev->master_mode = true; in stm32f7_i2c_xfer_msg()
986 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer_msg()
987 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer_msg()
988 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_xfer_msg()
992 f7_msg->result = 0; in stm32f7_i2c_smbus_xfer_msg()
993 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_smbus_xfer_msg()
1000 if (f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
1003 /* Set slave address */ in stm32f7_i2c_smbus_xfer_msg()
1005 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_smbus_xfer_msg()
1007 f7_msg->smbus_buf[0] = command; in stm32f7_i2c_smbus_xfer_msg()
1008 switch (f7_msg->size) { in stm32f7_i2c_smbus_xfer_msg()
1010 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1011 f7_msg->count = 0; in stm32f7_i2c_smbus_xfer_msg()
1014 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1015 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1018 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1019 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1020 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1023 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1024 f7_msg->count = 2; in stm32f7_i2c_smbus_xfer_msg()
1025 f7_msg->smbus_buf[1] = data->byte; in stm32f7_i2c_smbus_xfer_msg()
1029 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1030 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1031 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1034 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1035 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1036 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1037 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1041 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1042 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1043 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1046 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1047 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || in stm32f7_i2c_smbus_xfer_msg()
1048 !data->block[0]) { in stm32f7_i2c_smbus_xfer_msg()
1050 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1051 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1053 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1054 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1055 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1059 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1060 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1061 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1062 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1064 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1067 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1068 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { in stm32f7_i2c_smbus_xfer_msg()
1070 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1071 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1073 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1074 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1075 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1077 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1081 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1083 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); in stm32f7_i2c_smbus_xfer_msg()
1084 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1087 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_xfer_msg()
1090 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { in stm32f7_i2c_smbus_xfer_msg()
1092 if (!f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1094 f7_msg->count++; in stm32f7_i2c_smbus_xfer_msg()
1103 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_xfer_msg()
1114 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_xfer_msg()
1115 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_smbus_xfer_msg()
1116 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_xfer_msg()
1118 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_xfer_msg()
1122 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_xfer_msg()
1124 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_xfer_msg()
1127 if (!i2c_dev->use_dma) { in stm32f7_i2c_smbus_xfer_msg()
1142 i2c_dev->master_mode = true; in stm32f7_i2c_smbus_xfer_msg()
1153 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_rep_start()
1154 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_rep_start()
1164 switch (f7_msg->size) { in stm32f7_i2c_smbus_rep_start()
1166 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1170 f7_msg->count = 2; in stm32f7_i2c_smbus_rep_start()
1174 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1179 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_rep_start()
1180 f7_msg->stop = true; in stm32f7_i2c_smbus_rep_start()
1185 f7_msg->count++; in stm32f7_i2c_smbus_rep_start()
1190 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_rep_start()
1206 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_rep_start()
1207 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && in stm32f7_i2c_smbus_rep_start()
1208 f7_msg->size != I2C_SMBUS_BLOCK_DATA && in stm32f7_i2c_smbus_rep_start()
1209 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { in stm32f7_i2c_smbus_rep_start()
1210 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_rep_start()
1212 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_rep_start()
1217 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_rep_start()
1219 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_rep_start()
1222 if (!i2c_dev->use_dma) in stm32f7_i2c_smbus_rep_start()
1237 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_check_pec()
1240 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); in stm32f7_i2c_smbus_check_pec()
1242 switch (f7_msg->size) { in stm32f7_i2c_smbus_check_pec()
1245 received_pec = f7_msg->smbus_buf[1]; in stm32f7_i2c_smbus_check_pec()
1249 received_pec = f7_msg->smbus_buf[2]; in stm32f7_i2c_smbus_check_pec()
1253 count = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_check_pec()
1254 received_pec = f7_msg->smbus_buf[count]; in stm32f7_i2c_smbus_check_pec()
1257 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); in stm32f7_i2c_smbus_check_pec()
1258 return -EINVAL; in stm32f7_i2c_smbus_check_pec()
1262 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", in stm32f7_i2c_smbus_check_pec()
1264 return -EBADMSG; in stm32f7_i2c_smbus_check_pec()
1270 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) in stm32f7_i2c_is_addr_match() argument
1274 if (!slave) in stm32f7_i2c_is_addr_match()
1277 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_is_addr_match()
1279 * For 10-bit addr, addcode = 11110XY with in stm32f7_i2c_is_addr_match()
1280 * X = Bit 9 of slave address in stm32f7_i2c_is_addr_match()
1281 * Y = Bit 8 of slave address in stm32f7_i2c_is_addr_match()
1283 addr = slave->addr >> 8; in stm32f7_i2c_is_addr_match()
1288 addr = slave->addr & 0x7f; in stm32f7_i2c_is_addr_match()
1298 struct i2c_client *slave = i2c_dev->slave_running; in stm32f7_i2c_slave_start() local
1299 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_start()
1303 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_start()
1304 /* Notify i2c slave that new read transfer is starting */ in stm32f7_i2c_slave_start()
1305 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); in stm32f7_i2c_slave_start()
1308 * Disable slave TX config in case of I2C combined message in stm32f7_i2c_slave_start()
1325 /* Notify i2c slave that new write transfer is starting */ in stm32f7_i2c_slave_start()
1326 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); in stm32f7_i2c_slave_start()
1328 /* Set reload mode to be able to ACK/NACK each received byte */ in stm32f7_i2c_slave_start()
1334 * Set Slave Byte Control to be able to ACK/NACK each data in stm32f7_i2c_slave_start()
1346 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_addr()
1350 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_addr()
1355 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { in stm32f7_i2c_slave_addr()
1356 i2c_dev->slave_running = i2c_dev->slave[i]; in stm32f7_i2c_slave_addr()
1357 i2c_dev->slave_dir = dir; in stm32f7_i2c_slave_addr()
1359 /* Start I2C slave processing */ in stm32f7_i2c_slave_addr()
1371 struct i2c_client *slave, int *id) in stm32f7_i2c_get_slave_id() argument
1376 if (i2c_dev->slave[i] == slave) { in stm32f7_i2c_get_slave_id()
1382 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); in stm32f7_i2c_get_slave_id()
1384 return -ENODEV; in stm32f7_i2c_get_slave_id()
1388 struct i2c_client *slave, int *id) in stm32f7_i2c_get_free_slave_id() argument
1390 struct device *dev = i2c_dev->dev; in stm32f7_i2c_get_free_slave_id()
1394 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) in stm32f7_i2c_get_free_slave_id()
1395 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address in stm32f7_i2c_get_free_slave_id()
1396 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only in stm32f7_i2c_get_free_slave_id()
1398 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { in stm32f7_i2c_get_free_slave_id()
1399 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) in stm32f7_i2c_get_free_slave_id()
1405 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { in stm32f7_i2c_get_free_slave_id()
1407 (slave->flags & I2C_CLIENT_TEN)) in stm32f7_i2c_get_free_slave_id()
1409 if (!i2c_dev->slave[i]) { in stm32f7_i2c_get_free_slave_id()
1416 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); in stm32f7_i2c_get_free_slave_id()
1418 return -EINVAL; in stm32f7_i2c_get_free_slave_id()
1426 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_registered()
1439 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_busy()
1448 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_isr_event()
1453 /* Slave transmitter mode */ in stm32f7_i2c_slave_isr_event()
1455 i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1463 /* Transfer Complete Reload for Slave receiver mode */ in stm32f7_i2c_slave_isr_event()
1469 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); in stm32f7_i2c_slave_isr_event()
1470 ret = i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1474 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1476 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1485 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); in stm32f7_i2c_slave_isr_event()
1494 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_isr_event()
1506 /* Notify i2c slave that a STOP flag has been detected */ in stm32f7_i2c_slave_isr_event()
1507 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); in stm32f7_i2c_slave_isr_event()
1509 i2c_dev->slave_running = NULL; in stm32f7_i2c_slave_isr_event()
1521 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_handle_isr_errs()
1522 u16 addr = f7_msg->addr; in stm32f7_i2c_handle_isr_errs()
1523 void __iomem *base = i2c_dev->base; in stm32f7_i2c_handle_isr_errs()
1524 struct device *dev = i2c_dev->dev; in stm32f7_i2c_handle_isr_errs()
1530 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_handle_isr_errs()
1531 f7_msg->result = -EIO; in stm32f7_i2c_handle_isr_errs()
1538 f7_msg->result = -EAGAIN; in stm32f7_i2c_handle_isr_errs()
1544 f7_msg->result = -EINVAL; in stm32f7_i2c_handle_isr_errs()
1550 i2c_handle_smbus_alert(i2c_dev->alert->ara); in stm32f7_i2c_handle_isr_errs()
1554 if (!i2c_dev->slave_running) { in stm32f7_i2c_handle_isr_errs()
1565 if (i2c_dev->use_dma) in stm32f7_i2c_handle_isr_errs()
1568 i2c_dev->master_mode = false; in stm32f7_i2c_handle_isr_errs()
1569 complete(&i2c_dev->complete); in stm32f7_i2c_handle_isr_errs()
1581 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event()
1584 * Check if the interrupt is for a slave device or related in stm32f7_i2c_isr_event()
1585 * to errors flags (in case of single it line mode) in stm32f7_i2c_isr_event()
1587 if (!i2c_dev->master_mode || in stm32f7_i2c_isr_event()
1588 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))) in stm32f7_i2c_isr_event()
1611 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event_thread()
1612 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_event_thread()
1616 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event_thread()
1618 if (!i2c_dev->master_mode) in stm32f7_i2c_isr_event_thread()
1622 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)) in stm32f7_i2c_isr_event_thread()
1627 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", in stm32f7_i2c_isr_event_thread()
1628 __func__, f7_msg->addr); in stm32f7_i2c_isr_event_thread()
1630 if (i2c_dev->use_dma) in stm32f7_i2c_isr_event_thread()
1632 f7_msg->result = -ENXIO; in stm32f7_i2c_isr_event_thread()
1636 if (f7_msg->smbus) in stm32f7_i2c_isr_event_thread()
1645 if (i2c_dev->use_dma && !f7_msg->result) { in stm32f7_i2c_isr_event_thread()
1646 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); in stm32f7_i2c_isr_event_thread()
1648 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); in stm32f7_i2c_isr_event_thread()
1650 f7_msg->result = -ETIMEDOUT; in stm32f7_i2c_isr_event_thread()
1653 if (f7_msg->stop) { in stm32f7_i2c_isr_event_thread()
1656 } else if (f7_msg->smbus) { in stm32f7_i2c_isr_event_thread()
1659 i2c_dev->msg_id++; in stm32f7_i2c_isr_event_thread()
1660 i2c_dev->msg++; in stm32f7_i2c_isr_event_thread()
1661 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event_thread()
1677 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event_thread()
1678 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event_thread()
1689 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_error_thread()
1696 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout); in stm32f7_i2c_wait_polling()
1702 if (completion_done(&i2c_dev->complete)) in stm32f7_i2c_wait_polling()
1713 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer_core()
1714 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_xfer_core()
1718 i2c_dev->msg = msgs; in stm32f7_i2c_xfer_core()
1719 i2c_dev->msg_num = num; in stm32f7_i2c_xfer_core()
1720 i2c_dev->msg_id = 0; in stm32f7_i2c_xfer_core()
1721 f7_msg->smbus = false; in stm32f7_i2c_xfer_core()
1723 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_xfer_core()
1733 if (!i2c_dev->atomic) in stm32f7_i2c_xfer_core()
1734 time_left = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_xfer_core()
1735 i2c_dev->adap.timeout); in stm32f7_i2c_xfer_core()
1739 ret = f7_msg->result; in stm32f7_i2c_xfer_core()
1741 if (i2c_dev->use_dma) in stm32f7_i2c_xfer_core()
1742 dmaengine_synchronize(dma->chan_using); in stm32f7_i2c_xfer_core()
1750 i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_xfer_core()
1755 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", in stm32f7_i2c_xfer_core()
1756 i2c_dev->msg->addr); in stm32f7_i2c_xfer_core()
1757 if (i2c_dev->use_dma) in stm32f7_i2c_xfer_core()
1758 dmaengine_terminate_sync(dma->chan_using); in stm32f7_i2c_xfer_core()
1760 ret = -ETIMEDOUT; in stm32f7_i2c_xfer_core()
1764 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_xfer_core()
1774 i2c_dev->atomic = false; in stm32f7_i2c_xfer()
1783 i2c_dev->atomic = true; in stm32f7_i2c_xfer_atomic()
1793 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer()
1794 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_smbus_xfer()
1795 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer()
1799 f7_msg->addr = addr; in stm32f7_i2c_smbus_xfer()
1800 f7_msg->size = size; in stm32f7_i2c_smbus_xfer()
1801 f7_msg->read_write = read_write; in stm32f7_i2c_smbus_xfer()
1802 f7_msg->smbus = true; in stm32f7_i2c_smbus_xfer()
1816 time_left = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_smbus_xfer()
1817 i2c_dev->adap.timeout); in stm32f7_i2c_smbus_xfer()
1818 ret = f7_msg->result; in stm32f7_i2c_smbus_xfer()
1820 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1821 dmaengine_synchronize(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1829 i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_smbus_xfer()
1834 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); in stm32f7_i2c_smbus_xfer()
1835 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1836 dmaengine_terminate_sync(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1838 ret = -ETIMEDOUT; in stm32f7_i2c_smbus_xfer()
1853 data->byte = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_xfer()
1857 data->word = f7_msg->smbus_buf[0] | in stm32f7_i2c_smbus_xfer()
1858 (f7_msg->smbus_buf[1] << 8); in stm32f7_i2c_smbus_xfer()
1862 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) in stm32f7_i2c_smbus_xfer()
1863 data->block[i] = f7_msg->smbus_buf[i]; in stm32f7_i2c_smbus_xfer()
1867 ret = -EINVAL; in stm32f7_i2c_smbus_xfer()
1879 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_wakeup()
1882 if (!i2c_dev->wakeup_src) in stm32f7_i2c_enable_wakeup()
1886 device_set_wakeup_enable(i2c_dev->dev, true); in stm32f7_i2c_enable_wakeup()
1889 device_set_wakeup_enable(i2c_dev->dev, false); in stm32f7_i2c_enable_wakeup()
1894 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) in stm32f7_i2c_reg_slave() argument
1896 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_reg_slave()
1897 void __iomem *base = i2c_dev->base; in stm32f7_i2c_reg_slave()
1898 struct device *dev = i2c_dev->dev; in stm32f7_i2c_reg_slave()
1902 if (slave->flags & I2C_CLIENT_PEC) { in stm32f7_i2c_reg_slave()
1903 dev_err(dev, "SMBus PEC not supported in slave mode\n"); in stm32f7_i2c_reg_slave()
1904 return -EINVAL; in stm32f7_i2c_reg_slave()
1908 dev_err(dev, "Too much slave registered\n"); in stm32f7_i2c_reg_slave()
1909 return -EBUSY; in stm32f7_i2c_reg_slave()
1912 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); in stm32f7_i2c_reg_slave()
1925 /* Slave SMBus Host */ in stm32f7_i2c_reg_slave()
1926 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1931 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1933 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1934 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); in stm32f7_i2c_reg_slave()
1937 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); in stm32f7_i2c_reg_slave()
1940 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1941 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1946 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1948 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1949 ret = -EOPNOTSUPP; in stm32f7_i2c_reg_slave()
1953 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); in stm32f7_i2c_reg_slave()
1955 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1956 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1960 dev_err(dev, "I2C slave id not supported\n"); in stm32f7_i2c_reg_slave()
1961 ret = -ENODEV; in stm32f7_i2c_reg_slave()
1983 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) in stm32f7_i2c_unreg_slave() argument
1985 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_unreg_slave()
1986 void __iomem *base = i2c_dev->base; in stm32f7_i2c_unreg_slave()
1990 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); in stm32f7_i2c_unreg_slave()
1994 WARN_ON(!i2c_dev->slave[id]); in stm32f7_i2c_unreg_slave()
1996 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
2008 i2c_dev->slave[id] = NULL; in stm32f7_i2c_unreg_slave()
2015 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
2025 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || in stm32f7_i2c_write_fm_plus_bits()
2026 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap))) in stm32f7_i2c_write_fm_plus_bits()
2030 if (i2c_dev->setup.fmp_cr1_bit) { in stm32f7_i2c_write_fm_plus_bits()
2032 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); in stm32f7_i2c_write_fm_plus_bits()
2034 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); in stm32f7_i2c_write_fm_plus_bits()
2036 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) in stm32f7_i2c_write_fm_plus_bits()
2037 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg, in stm32f7_i2c_write_fm_plus_bits()
2038 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0); in stm32f7_i2c_write_fm_plus_bits()
2040 ret = regmap_write(i2c_dev->regmap, in stm32f7_i2c_write_fm_plus_bits()
2041 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg, in stm32f7_i2c_write_fm_plus_bits()
2042 i2c_dev->fmp_mask); in stm32f7_i2c_write_fm_plus_bits()
2051 struct device_node *np = pdev->dev.of_node; in stm32f7_i2c_setup_fm_plus_bits()
2054 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); in stm32f7_i2c_setup_fm_plus_bits()
2055 if (IS_ERR(i2c_dev->regmap)) in stm32f7_i2c_setup_fm_plus_bits()
2059 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, in stm32f7_i2c_setup_fm_plus_bits()
2060 &i2c_dev->fmp_sreg); in stm32f7_i2c_setup_fm_plus_bits()
2064 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + in stm32f7_i2c_setup_fm_plus_bits()
2065 i2c_dev->setup.fmp_clr_offset; in stm32f7_i2c_setup_fm_plus_bits()
2067 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, in stm32f7_i2c_setup_fm_plus_bits()
2068 &i2c_dev->fmp_mask); in stm32f7_i2c_setup_fm_plus_bits()
2073 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_host()
2074 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_host()
2081 i2c_dev->host_notify_client = client; in stm32f7_i2c_enable_smbus_host()
2091 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_host()
2093 if (i2c_dev->host_notify_client) { in stm32f7_i2c_disable_smbus_host()
2097 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); in stm32f7_i2c_disable_smbus_host()
2104 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_alert()
2105 struct device *dev = i2c_dev->dev; in stm32f7_i2c_enable_smbus_alert()
2106 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_alert()
2110 return -ENOMEM; in stm32f7_i2c_enable_smbus_alert()
2112 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); in stm32f7_i2c_enable_smbus_alert()
2113 if (IS_ERR(alert->ara)) in stm32f7_i2c_enable_smbus_alert()
2114 return PTR_ERR(alert->ara); in stm32f7_i2c_enable_smbus_alert()
2116 i2c_dev->alert = alert; in stm32f7_i2c_enable_smbus_alert()
2126 struct stm32f7_i2c_alert *alert = i2c_dev->alert; in stm32f7_i2c_disable_smbus_alert()
2127 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_alert()
2133 i2c_unregister_device(alert->ara); in stm32f7_i2c_disable_smbus_alert()
2148 if (i2c_dev->smbus_mode) in stm32f7_i2c_func()
2173 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in stm32f7_i2c_probe()
2175 return -ENOMEM; in stm32f7_i2c_probe()
2177 setup = of_device_get_match_data(&pdev->dev); in stm32f7_i2c_probe()
2179 dev_err(&pdev->dev, "Can't get device data\n"); in stm32f7_i2c_probe()
2180 return -ENODEV; in stm32f7_i2c_probe()
2182 i2c_dev->setup = *setup; in stm32f7_i2c_probe()
2184 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32f7_i2c_probe()
2185 if (IS_ERR(i2c_dev->base)) in stm32f7_i2c_probe()
2186 return PTR_ERR(i2c_dev->base); in stm32f7_i2c_probe()
2187 phy_addr = (dma_addr_t)res->start; in stm32f7_i2c_probe()
2193 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, in stm32f7_i2c_probe()
2194 "wakeup-source"); in stm32f7_i2c_probe()
2196 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); in stm32f7_i2c_probe()
2197 if (IS_ERR(i2c_dev->clk)) in stm32f7_i2c_probe()
2198 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), in stm32f7_i2c_probe()
2201 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
2203 return dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32f7_i2c_probe()
2210 i2c_dev->dev = &pdev->dev; in stm32f7_i2c_probe()
2212 ret = devm_request_threaded_irq(&pdev->dev, irq_event, in stm32f7_i2c_probe()
2216 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2218 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n"); in stm32f7_i2c_probe()
2220 if (!i2c_dev->setup.single_it_line) { in stm32f7_i2c_probe()
2225 ret = devm_request_threaded_irq(&pdev->dev, irq_error, in stm32f7_i2c_probe()
2229 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2231 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n"); in stm32f7_i2c_probe()
2234 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); in stm32f7_i2c_probe()
2238 /* Setup Fast mode plus if necessary */ in stm32f7_i2c_probe()
2239 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { in stm32f7_i2c_probe()
2240 if (!i2c_dev->setup.fmp_cr1_bit) { in stm32f7_i2c_probe()
2251 adap = &i2c_dev->adap; in stm32f7_i2c_probe()
2253 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", in stm32f7_i2c_probe()
2254 &res->start); in stm32f7_i2c_probe()
2255 adap->owner = THIS_MODULE; in stm32f7_i2c_probe()
2256 adap->timeout = 2 * HZ; in stm32f7_i2c_probe()
2257 adap->retries = 3; in stm32f7_i2c_probe()
2258 adap->algo = &stm32f7_i2c_algo; in stm32f7_i2c_probe()
2259 adap->dev.parent = &pdev->dev; in stm32f7_i2c_probe()
2260 adap->dev.of_node = pdev->dev.of_node; in stm32f7_i2c_probe()
2262 init_completion(&i2c_dev->complete); in stm32f7_i2c_probe()
2265 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, in stm32f7_i2c_probe()
2268 if (IS_ERR(i2c_dev->dma)) { in stm32f7_i2c_probe()
2269 ret = PTR_ERR(i2c_dev->dma); in stm32f7_i2c_probe()
2271 if (ret != -ENODEV) in stm32f7_i2c_probe()
2273 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); in stm32f7_i2c_probe()
2274 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2277 if (i2c_dev->wakeup_src) { in stm32f7_i2c_probe()
2278 device_set_wakeup_capable(i2c_dev->dev, true); in stm32f7_i2c_probe()
2280 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); in stm32f7_i2c_probe()
2282 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); in stm32f7_i2c_probe()
2289 pm_runtime_set_autosuspend_delay(i2c_dev->dev, in stm32f7_i2c_probe()
2291 pm_runtime_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2292 pm_runtime_set_active(i2c_dev->dev); in stm32f7_i2c_probe()
2293 pm_runtime_enable(i2c_dev->dev); in stm32f7_i2c_probe()
2295 pm_runtime_get_noresume(&pdev->dev); in stm32f7_i2c_probe()
2299 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); in stm32f7_i2c_probe()
2305 if (i2c_dev->smbus_mode) { in stm32f7_i2c_probe()
2308 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2309 "failed to enable SMBus Host-Notify protocol (%d)\n", in stm32f7_i2c_probe()
2315 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { in stm32f7_i2c_probe()
2318 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2325 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); in stm32f7_i2c_probe()
2327 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2338 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_probe()
2339 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_probe()
2340 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_probe()
2341 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2343 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2344 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_probe()
2347 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2348 device_set_wakeup_capable(i2c_dev->dev, false); in stm32f7_i2c_probe()
2350 if (i2c_dev->dma) { in stm32f7_i2c_probe()
2351 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_probe()
2352 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2368 i2c_del_adapter(&i2c_dev->adap); in stm32f7_i2c_remove()
2369 pm_runtime_get_sync(i2c_dev->dev); in stm32f7_i2c_remove()
2371 if (i2c_dev->wakeup_src) { in stm32f7_i2c_remove()
2372 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_remove()
2377 device_init_wakeup(i2c_dev->dev, false); in stm32f7_i2c_remove()
2380 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_remove()
2381 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_remove()
2382 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_remove()
2383 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_remove()
2385 if (i2c_dev->dma) { in stm32f7_i2c_remove()
2386 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_remove()
2387 i2c_dev->dma = NULL; in stm32f7_i2c_remove()
2398 clk_disable(i2c_dev->clk); in stm32f7_i2c_runtime_suspend()
2409 ret = clk_enable(i2c_dev->clk); in stm32f7_i2c_runtime_resume()
2422 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_backup()
2424 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2428 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_backup()
2429 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_backup()
2430 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_backup()
2431 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_backup()
2432 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_backup()
2435 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2444 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_restore()
2446 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2450 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2452 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2455 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_restore()
2456 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, in stm32f7_i2c_regs_restore()
2457 i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2458 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) in stm32f7_i2c_regs_restore()
2459 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2461 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_restore()
2462 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_restore()
2463 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_restore()
2466 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2476 i2c_mark_adapter_suspended(&i2c_dev->adap); in stm32f7_i2c_suspend()
2481 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_suspend()
2508 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_resume()
2520 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2521 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2522 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2523 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup},
2530 .name = "stm32f7-i2c",