Lines Matching +full:rx +full:- +full:fifo +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
78 /* Most significant word offset in FIFO port */
151 /* TAG length for DATA READ in RX FIFO */
164 * rx_tag_len: rx tag length for current block
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
169 * tx_fifo_data_pos: current byte number in TX FIFO word
171 * rx_fifo_data_pos: current byte number in RX FIFO word
172 * fifo_available: number of available bytes in RX FIFO for current
174 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
175 * to TX FIFO will be appended in this data and will be written to
176 * TX FIFO when all the 4 bytes are available.
177 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
178 * contains the 4 bytes of RX data.
181 * tx_tags_sent: all tx tag bytes have been written in FIFO word
182 * send_last_word: for tx FIFO, last word send is pending in current block
183 * rx_bytes_read: if all the bytes have been read from rx FIFO.
184 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
185 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
186 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
280 /* function to write data in tx fifo */
282 /* function to read data from rx fifo */
284 /* function to write tags in tx fifo for i2c read transfer */
291 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
296 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
297 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
298 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
300 if (!qup->msg) { in qup_i2c_interrupt()
302 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
311 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
315 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
322 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
331 * HW FIFO and generates the BAM interrupt. in qup_i2c_interrupt()
333 if (!qup->use_dma) in qup_i2c_interrupt()
334 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
339 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
342 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
343 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
344 qup->write_rx_tags(qup); in qup_i2c_interrupt()
346 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
351 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
353 if (!blk->is_rx_blk_mode) { in qup_i2c_interrupt()
354 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
355 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
357 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
358 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
362 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
363 if (!blk->rx_bytes_read) in qup_i2c_interrupt()
368 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags in qup_i2c_interrupt()
370 * of interrupt for write message in FIFO mode is in qup_i2c_interrupt()
373 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) in qup_i2c_interrupt()
378 qup->qup_err = qup_err; in qup_i2c_interrupt()
379 qup->bus_err = bus_err; in qup_i2c_interrupt()
380 complete(&qup->xfer); in qup_i2c_interrupt()
395 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
402 } while (retries--); in qup_i2c_poll_state_mask()
404 return -ETIMEDOUT; in qup_i2c_poll_state_mask()
414 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
417 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
433 return -EIO; in qup_i2c_change_state()
435 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
438 return -EIO; in qup_i2c_change_state()
451 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
456 ret = -ETIMEDOUT; in qup_i2c_bus_active()
471 if (qup->cur_bw_clk_freq == clk_freq) in qup_i2c_vote_bw()
475 ret = icc_set_bw(qup->icc_path, 0, needed_peak_bw); in qup_i2c_vote_bw()
479 qup->cur_bw_clk_freq = clk_freq; in qup_i2c_vote_bw()
485 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
486 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
492 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
495 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
501 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
502 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
508 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
510 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
513 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
514 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
516 qup->pos++; in qup_i2c_write_tx_fifo_v1()
518 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
525 qup->blk.pos = 0; in qup_i2c_set_blk_data()
526 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
527 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
534 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
535 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
537 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
544 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); in qup_i2c_check_msg_len()
552 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
559 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags_smb()
576 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
582 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
586 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags()
592 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
597 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
598 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
621 complete(&qup->xfer); in qup_i2c_bam_cb()
631 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
633 return -EINVAL; in qup_sg_set_buf()
640 if (qup->btx.dma) in qup_i2c_rel_dma()
641 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
642 if (qup->brx.dma) in qup_i2c_rel_dma()
643 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
644 qup->btx.dma = NULL; in qup_i2c_rel_dma()
645 qup->brx.dma = NULL; in qup_i2c_rel_dma()
652 if (!qup->btx.dma) { in qup_i2c_req_dma()
653 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
654 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
655 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
656 qup->btx.dma = NULL; in qup_i2c_req_dma()
657 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
662 if (!qup->brx.dma) { in qup_i2c_req_dma()
663 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
664 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
665 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
666 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
667 qup->brx.dma = NULL; in qup_i2c_req_dma()
682 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
685 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
686 rem = msg->len - (blocks - 1) * limit; in qup_i2c_bam_make_desc()
688 if (msg->flags & I2C_M_RD) { in qup_i2c_bam_make_desc()
689 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
690 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
691 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
693 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
696 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
697 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
703 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
704 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
711 qup->blk.pos = i; in qup_i2c_bam_make_desc()
713 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
714 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
719 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
721 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
722 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
723 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
725 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
727 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
734 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
735 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
740 qup->blk.pos = i; in qup_i2c_bam_make_desc()
743 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
755 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
760 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
764 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
765 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
771 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
772 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
777 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
781 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
782 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
787 txd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
788 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
793 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
797 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
800 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
804 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
805 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
808 dmaengine_terminate_sync(qup->btx.dma); in qup_i2c_bam_schedule_desc()
812 rxd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
813 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
816 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
820 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
823 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) in qup_i2c_bam_schedule_desc()
824 ret = -ETIMEDOUT; in qup_i2c_bam_schedule_desc()
826 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
827 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
831 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
838 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
839 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
841 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
845 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
848 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
856 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
857 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
858 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
868 ret = qup_i2c_vote_bw(qup, qup->src_clk_freq); in qup_i2c_bam_xfer()
872 enable_irq(qup->irq); in qup_i2c_bam_xfer()
878 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
879 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
882 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
884 /* mask fifo irqs */ in qup_i2c_bam_xfer()
885 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
892 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
896 qup->msg = msg + idx; in qup_i2c_bam_xfer()
897 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
899 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
910 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
911 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
912 qup->is_last) { in qup_i2c_bam_xfer()
922 disable_irq(qup->irq); in qup_i2c_bam_xfer()
924 qup->msg = NULL; in qup_i2c_bam_xfer()
934 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
936 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
937 ret = -ETIMEDOUT; in qup_i2c_wait_for_complete()
940 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
941 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
948 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
949 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
953 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
956 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
957 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
959 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
962 blk->fifo_available--; in qup_i2c_read_rx_fifo_v1()
965 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
966 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v1()
971 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
977 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; in qup_i2c_write_rx_tags_v1()
980 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
985 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
989 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
990 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
992 if (blk->is_tx_blk_mode) { in qup_i2c_conf_v1()
994 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
995 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
997 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
998 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
1001 if (blk->total_rx_len) { in qup_i2c_conf_v1()
1002 if (blk->is_rx_blk_mode) { in qup_i2c_conf_v1()
1004 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1005 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1007 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1008 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1014 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
1015 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
1020 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v1()
1021 blk->fifo_available = 0; in qup_i2c_clear_blk_v1()
1022 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v1()
1027 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1036 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1042 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1043 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1044 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v1()
1045 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1057 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1064 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1070 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1071 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1073 qup->pos = 0; in qup_i2c_write_one()
1074 blk->total_tx_len = msg->len + 1; in qup_i2c_write_one()
1075 blk->total_rx_len = 0; in qup_i2c_write_one()
1082 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1084 qup->pos = 0; in qup_i2c_read_one()
1085 blk->total_tx_len = 2; in qup_i2c_read_one()
1086 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1098 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1102 qup->bus_err = 0; in qup_i2c_xfer()
1103 qup->qup_err = 0; in qup_i2c_xfer()
1105 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1111 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1115 ret = -EIO; in qup_i2c_xfer()
1120 ret = -EINVAL; in qup_i2c_xfer()
1124 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1142 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1153 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1156 if (blk->is_tx_blk_mode) in qup_i2c_conf_count_v2()
1157 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1158 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1160 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1161 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1163 if (blk->total_rx_len) { in qup_i2c_conf_count_v2()
1164 if (blk->is_rx_blk_mode) in qup_i2c_conf_count_v2()
1165 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1166 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1168 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1169 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1174 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1178 * Configure registers related with transfer mode (FIFO/Block)
1184 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1187 if (blk->is_tx_blk_mode) { in qup_i2c_conf_mode_v2()
1189 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1191 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1194 if (blk->is_rx_blk_mode) { in qup_i2c_conf_mode_v2()
1196 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1198 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1201 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1207 blk->send_last_word = false; in qup_i2c_clear_blk_v2()
1208 blk->tx_tags_sent = false; in qup_i2c_clear_blk_v2()
1209 blk->tx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1210 blk->tx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1211 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v2()
1213 blk->rx_tags_fetched = false; in qup_i2c_clear_blk_v2()
1214 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v2()
1215 blk->rx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1216 blk->rx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1217 blk->fifo_available = 0; in qup_i2c_clear_blk_v2()
1220 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1223 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1226 for (j = blk->rx_fifo_data_pos; in qup_i2c_recv_data()
1227 blk->cur_blk_len && blk->fifo_available; in qup_i2c_recv_data()
1228 blk->cur_blk_len--, blk->fifo_available--) { in qup_i2c_recv_data()
1230 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1232 *(blk->cur_data++) = blk->rx_fifo_data; in qup_i2c_recv_data()
1233 blk->rx_fifo_data >>= 8; in qup_i2c_recv_data()
1241 blk->rx_fifo_data_pos = j; in qup_i2c_recv_data()
1247 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1249 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1250 blk->rx_fifo_data >>= blk->rx_tag_len * 8; in qup_i2c_recv_tags()
1251 blk->rx_fifo_data_pos = blk->rx_tag_len; in qup_i2c_recv_tags()
1252 blk->fifo_available -= blk->rx_tag_len; in qup_i2c_recv_tags()
1256 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1260 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1265 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1267 if (!blk->rx_tags_fetched) { in qup_i2c_read_rx_fifo_v2()
1269 blk->rx_tags_fetched = true; in qup_i2c_read_rx_fifo_v2()
1273 if (!blk->cur_blk_len) in qup_i2c_read_rx_fifo_v2()
1274 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v2()
1278 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1279 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1280 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1285 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1288 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; in qup_i2c_write_blk_data()
1289 (*len)--, blk->tx_fifo_free--) { in qup_i2c_write_blk_data()
1290 blk->tx_fifo_data |= *(*data)++ << (j * 8); in qup_i2c_write_blk_data()
1292 writel(blk->tx_fifo_data, in qup_i2c_write_blk_data()
1293 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1294 blk->tx_fifo_data = 0x0; in qup_i2c_write_blk_data()
1301 blk->tx_fifo_data_pos = j; in qup_i2c_write_blk_data()
1307 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1309 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1310 if (blk->tx_fifo_data_pos) in qup_i2c_write_rx_tags_v2()
1311 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1315 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1319 * tags to TX FIFO and set tx_tags_sent to true.
1321 * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO
1323 * in FIFO.
1324 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1327 * have been written in TX FIFO so nothing else is required.
1328 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1329 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1330 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1334 * FIFO full so make send_last_word true.
1338 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1340 if (!blk->tx_tags_sent) { in qup_i2c_write_tx_fifo_v2()
1341 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1342 &blk->tx_tag_len); in qup_i2c_write_tx_fifo_v2()
1343 blk->tx_tags_sent = true; in qup_i2c_write_tx_fifo_v2()
1346 if (blk->send_last_word) in qup_i2c_write_tx_fifo_v2()
1349 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1350 if (!blk->cur_blk_len) { in qup_i2c_write_tx_fifo_v2()
1351 if (!blk->tx_fifo_data_pos) in qup_i2c_write_tx_fifo_v2()
1354 if (blk->tx_fifo_free) in qup_i2c_write_tx_fifo_v2()
1357 blk->send_last_word = true; in qup_i2c_write_tx_fifo_v2()
1363 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1375 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1376 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1385 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1391 blk->cur_data += 1; in qup_i2c_conf_xfer_v2()
1398 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1409 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1416 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1417 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1419 * In FIFO mode, tx FIFO can be written directly while in block mode the in qup_i2c_conf_xfer_v2()
1422 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v2()
1423 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1447 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1460 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1461 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1462 u8 *msg_buf = msg->buf; in qup_i2c_xfer_v2_msg()
1464 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1467 for (i = 0; i < blk->count; i++) { in qup_i2c_xfer_v2_msg()
1469 blk->pos = i; in qup_i2c_xfer_v2_msg()
1470 blk->cur_tx_tags = blk->tags; in qup_i2c_xfer_v2_msg()
1471 blk->cur_blk_len = data_len; in qup_i2c_xfer_v2_msg()
1472 blk->tx_tag_len = in qup_i2c_xfer_v2_msg()
1473 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1475 blk->cur_data = msg_buf; in qup_i2c_xfer_v2_msg()
1478 blk->total_tx_len = blk->tx_tag_len; in qup_i2c_xfer_v2_msg()
1479 blk->rx_tag_len = 2; in qup_i2c_xfer_v2_msg()
1480 blk->total_rx_len = blk->rx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1482 blk->total_tx_len = blk->tx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1483 blk->total_rx_len = 0; in qup_i2c_xfer_v2_msg()
1487 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1492 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && in qup_i2c_xfer_v2_msg()
1493 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1494 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) in qup_i2c_xfer_v2_msg()
1495 return -EPROTO; in qup_i2c_xfer_v2_msg()
1497 msg->len = msg->buf[0]; in qup_i2c_xfer_v2_msg()
1498 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1500 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1504 msg->len += 1; in qup_i2c_xfer_v2_msg()
1508 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1516 * Programmed IO using FIFO mode : Less than FIFO size
1517 * Programmed IO using Block mode : Greater than FIFO size
1518 * DMA using BAM : Appropriate for any transaction size but the address should
1524 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1525 * 2. If complete transfer length is greater than fifo size then use the DMA
1527 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1528 * for maximum tx and rx length to determine mode.
1553 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1554 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1555 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1557 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1559 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1573 qup->bus_err = 0; in qup_i2c_xfer_v2()
1574 qup->qup_err = 0; in qup_i2c_xfer_v2()
1576 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1584 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1590 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1591 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1594 ret = -EIO; in qup_i2c_xfer_v2()
1598 if (qup->use_dma) { in qup_i2c_xfer_v2()
1599 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1601 qup->use_dma = false; in qup_i2c_xfer_v2()
1606 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1607 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1614 qup->msg = NULL; in qup_i2c_xfer_v2()
1626 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1662 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1663 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1671 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1672 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1674 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1676 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1690 u32 io_mode, hw_ver, size; in qup_i2c_probe() local
1697 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1699 return -ENOMEM; in qup_i2c_probe()
1701 qup->dev = &pdev->dev; in qup_i2c_probe()
1702 init_completion(&qup->xfer); in qup_i2c_probe()
1706 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1709 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1711 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1716 if (device_is_compatible(&pdev->dev, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1717 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1718 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1721 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1722 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1724 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1729 if (ret == -EPROBE_DEFER) in qup_i2c_probe()
1734 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1736 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1737 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1739 if (!qup->btx.sg) { in qup_i2c_probe()
1740 ret = -ENOMEM; in qup_i2c_probe()
1743 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1745 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1746 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1748 if (!qup->brx.sg) { in qup_i2c_probe()
1749 ret = -ENOMEM; in qup_i2c_probe()
1752 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1755 size = blocks * 2 + 5; in qup_i2c_probe()
1757 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1758 size, GFP_KERNEL); in qup_i2c_probe()
1759 if (!qup->start_tag.start) { in qup_i2c_probe()
1760 ret = -ENOMEM; in qup_i2c_probe()
1764 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1765 if (!qup->brx.tag.start) { in qup_i2c_probe()
1766 ret = -ENOMEM; in qup_i2c_probe()
1770 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1771 if (!qup->btx.tag.start) { in qup_i2c_probe()
1772 ret = -ENOMEM; in qup_i2c_probe()
1775 qup->is_dma = true; in qup_i2c_probe()
1777 qup->icc_path = devm_of_icc_get(&pdev->dev, NULL); in qup_i2c_probe()
1778 if (IS_ERR(qup->icc_path)) in qup_i2c_probe()
1779 return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path), in qup_i2c_probe()
1786 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1788 ret = -EINVAL; in qup_i2c_probe()
1792 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1793 if (IS_ERR(qup->base)) { in qup_i2c_probe()
1794 ret = PTR_ERR(qup->base); in qup_i2c_probe()
1798 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1799 if (qup->irq < 0) { in qup_i2c_probe()
1800 ret = qup->irq; in qup_i2c_probe()
1804 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1805 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1806 "src-clock-hz", &src_clk_freq); in qup_i2c_probe()
1808 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1811 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1813 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1814 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1815 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1816 ret = PTR_ERR(qup->clk); in qup_i2c_probe()
1820 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1821 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1822 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1823 ret = PTR_ERR(qup->pclk); in qup_i2c_probe()
1827 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1829 qup->src_clk_freq = src_clk_freq; in qup_i2c_probe()
1835 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1840 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1844 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1848 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1849 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1851 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1854 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' in qup_i2c_probe()
1857 size = QUP_OUTPUT_BLOCK_SIZE(io_mode); in qup_i2c_probe()
1858 if (size >= ARRAY_SIZE(blk_sizes)) { in qup_i2c_probe()
1859 ret = -EIO; in qup_i2c_probe()
1862 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1864 size = QUP_INPUT_BLOCK_SIZE(io_mode); in qup_i2c_probe()
1865 if (size >= ARRAY_SIZE(blk_sizes)) { in qup_i2c_probe()
1866 ret = -EIO; in qup_i2c_probe()
1869 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1874 * single transfer but the block size is in bytes so divide the in qup_i2c_probe()
1877 qup->in_blk_sz /= 2; in qup_i2c_probe()
1878 qup->out_blk_sz /= 2; in qup_i2c_probe()
1879 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1880 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1881 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1883 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1884 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1885 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1888 size = QUP_OUTPUT_FIFO_SIZE(io_mode); in qup_i2c_probe()
1889 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1891 size = QUP_INPUT_FIFO_SIZE(io_mode); in qup_i2c_probe()
1892 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1896 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; in qup_i2c_probe()
1897 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1900 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; in qup_i2c_probe()
1901 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1909 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1910 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1911 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1913 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1914 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1915 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1917 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1918 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1919 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1920 qup->is_last = true; in qup_i2c_probe()
1922 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1924 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1925 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1926 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1927 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1929 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1936 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1937 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1941 if (qup->btx.dma) in qup_i2c_probe()
1942 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1943 if (qup->brx.dma) in qup_i2c_probe()
1944 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1952 if (qup->is_dma) { in qup_i2c_remove()
1953 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1954 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1957 disable_irq(qup->irq); in qup_i2c_remove()
1959 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1960 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1961 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
2003 { .compatible = "qcom,i2c-qup-v1.1.1" },
2004 { .compatible = "qcom,i2c-qup-v2.1.1" },
2005 { .compatible = "qcom,i2c-qup-v2.2.1" },