Lines Matching +full:qup +full:- +full:memory
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
26 /* QUP Registers */
46 /* QUP States and reset values */
59 /* QUP OPERATIONAL FLAGS */
98 /* QUP tags */
106 /* QUP v2 tags */
145 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
170 * tx_fifo_free: number of free bytes in current QUP block write.
173 * QUP block read
174 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
177 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
187 * tags: contains tx tag bytes for current QUP transfer
252 /* QUP core errors */
281 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
283 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
285 void (*write_rx_tags)(struct qup_i2c_dev *qup);
290 struct qup_i2c_dev *qup = dev; in qup_i2c_interrupt() local
291 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
296 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
297 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
298 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
300 if (!qup->msg) { in qup_i2c_interrupt()
302 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
311 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
315 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
319 * transfer. In Error case, sometimes, QUP generates more than one in qup_i2c_interrupt()
322 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
325 /* Reset the QUP State in case of error */ in qup_i2c_interrupt()
328 * Don’t reset the QUP state in case of BAM mode. The BAM in qup_i2c_interrupt()
333 if (!qup->use_dma) in qup_i2c_interrupt()
334 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
339 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
342 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
343 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
344 qup->write_rx_tags(qup); in qup_i2c_interrupt()
346 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
351 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
353 if (!blk->is_rx_blk_mode) { in qup_i2c_interrupt()
354 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
355 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
357 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
358 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
362 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
363 if (!blk->rx_bytes_read) in qup_i2c_interrupt()
373 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) in qup_i2c_interrupt()
378 qup->qup_err = qup_err; in qup_i2c_interrupt()
379 qup->bus_err = bus_err; in qup_i2c_interrupt()
380 complete(&qup->xfer); in qup_i2c_interrupt()
384 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, in qup_i2c_poll_state_mask() argument
395 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
402 } while (retries--); in qup_i2c_poll_state_mask()
404 return -ETIMEDOUT; in qup_i2c_poll_state_mask()
407 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) in qup_i2c_poll_state() argument
409 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); in qup_i2c_poll_state()
412 static void qup_i2c_flush(struct qup_i2c_dev *qup) in qup_i2c_flush() argument
414 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
417 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
420 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) in qup_i2c_poll_state_valid() argument
422 return qup_i2c_poll_state_mask(qup, 0, 0); in qup_i2c_poll_state_valid()
425 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) in qup_i2c_poll_state_i2c_master() argument
427 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); in qup_i2c_poll_state_i2c_master()
430 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) in qup_i2c_change_state() argument
432 if (qup_i2c_poll_state_valid(qup) != 0) in qup_i2c_change_state()
433 return -EIO; in qup_i2c_change_state()
435 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
437 if (qup_i2c_poll_state(qup, state) != 0) in qup_i2c_change_state()
438 return -EIO; in qup_i2c_change_state()
443 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) in qup_i2c_bus_active() argument
451 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
456 ret = -ETIMEDOUT; in qup_i2c_bus_active()
464 static int qup_i2c_vote_bw(struct qup_i2c_dev *qup, u32 clk_freq) in qup_i2c_vote_bw() argument
469 if (qup->cur_bw_clk_freq == clk_freq) in qup_i2c_vote_bw()
473 ret = icc_set_bw(qup->icc_path, 0, needed_peak_bw); in qup_i2c_vote_bw()
477 qup->cur_bw_clk_freq = clk_freq; in qup_i2c_vote_bw()
481 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) in qup_i2c_write_tx_fifo_v1() argument
483 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
484 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
490 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
493 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
499 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
500 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
506 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
508 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
511 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
512 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
514 qup->pos++; in qup_i2c_write_tx_fifo_v1()
516 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
520 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, in qup_i2c_set_blk_data() argument
523 qup->blk.pos = 0; in qup_i2c_set_blk_data()
524 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
525 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
528 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) in qup_i2c_get_data_len() argument
532 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
533 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
535 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
542 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); in qup_i2c_check_msg_len()
545 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, in qup_i2c_set_tags_smb() argument
550 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
552 tags[len++] = qup_i2c_get_data_len(qup); in qup_i2c_set_tags_smb()
557 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags_smb()
567 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, in qup_i2c_set_tags() argument
574 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
578 return qup_i2c_set_tags_smb(addr, tags, qup, msg); in qup_i2c_set_tags()
580 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
584 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags()
590 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
595 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
596 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
603 data_len = qup_i2c_get_data_len(qup); in qup_i2c_set_tags()
617 struct qup_i2c_dev *qup = data; in qup_i2c_bam_cb() local
619 complete(&qup->xfer); in qup_i2c_bam_cb()
623 unsigned int buflen, struct qup_i2c_dev *qup, in qup_sg_set_buf() argument
629 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
631 return -EINVAL; in qup_sg_set_buf()
636 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) in qup_i2c_rel_dma() argument
638 if (qup->btx.dma) in qup_i2c_rel_dma()
639 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
640 if (qup->brx.dma) in qup_i2c_rel_dma()
641 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
642 qup->btx.dma = NULL; in qup_i2c_rel_dma()
643 qup->brx.dma = NULL; in qup_i2c_rel_dma()
646 static int qup_i2c_req_dma(struct qup_i2c_dev *qup) in qup_i2c_req_dma() argument
650 if (!qup->btx.dma) { in qup_i2c_req_dma()
651 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
652 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
653 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
654 qup->btx.dma = NULL; in qup_i2c_req_dma()
655 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
660 if (!qup->brx.dma) { in qup_i2c_req_dma()
661 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
662 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
663 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
664 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
665 qup->brx.dma = NULL; in qup_i2c_req_dma()
666 qup_i2c_rel_dma(qup); in qup_i2c_req_dma()
673 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) in qup_i2c_bam_make_desc() argument
680 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
681 qup_i2c_set_blk_data(qup, msg); in qup_i2c_bam_make_desc()
683 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
684 rem = msg->len - (blocks - 1) * limit; in qup_i2c_bam_make_desc()
686 if (msg->flags & I2C_M_RD) { in qup_i2c_bam_make_desc()
687 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
688 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
689 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
690 len += qup_i2c_set_tags(tags, qup, msg); in qup_i2c_bam_make_desc()
691 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
694 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
695 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
696 2, qup, DMA_FROM_DEVICE); in qup_i2c_bam_make_desc()
701 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
702 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
703 tlen, qup, in qup_i2c_bam_make_desc()
709 qup->blk.pos = i; in qup_i2c_bam_make_desc()
711 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
712 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
713 len, qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
717 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
719 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
720 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
721 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
722 len = qup_i2c_set_tags(tags, qup, msg); in qup_i2c_bam_make_desc()
723 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
725 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
727 qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
732 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
733 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
734 tlen, qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
738 qup->blk.pos = i; in qup_i2c_bam_make_desc()
741 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
747 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) in qup_i2c_bam_schedule_desc() argument
753 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
758 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
762 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
763 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
764 1, qup, DMA_FROM_DEVICE); in qup_i2c_bam_schedule_desc()
769 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
770 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
771 len, qup, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
775 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
779 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
780 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
785 txd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
786 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
791 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
795 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
798 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
802 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
803 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
806 dmaengine_terminate_sync(qup->btx.dma); in qup_i2c_bam_schedule_desc()
810 rxd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
811 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
814 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
818 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
821 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) in qup_i2c_bam_schedule_desc()
822 ret = -ETIMEDOUT; in qup_i2c_bam_schedule_desc()
824 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
825 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
827 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_bam_schedule_desc()
829 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
833 qup_i2c_flush(qup); in qup_i2c_bam_schedule_desc()
836 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
837 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
839 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
843 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
846 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
852 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) in qup_i2c_bam_clear_tag_buffers() argument
854 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
855 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
856 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
862 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_bam_xfer() local
866 ret = qup_i2c_vote_bw(qup, qup->src_clk_freq); in qup_i2c_bam_xfer()
870 enable_irq(qup->irq); in qup_i2c_bam_xfer()
871 ret = qup_i2c_req_dma(qup); in qup_i2c_bam_xfer()
876 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
877 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
880 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
883 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
886 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_bam_xfer()
890 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
891 qup_i2c_bam_clear_tag_buffers(qup); in qup_i2c_bam_xfer()
894 qup->msg = msg + idx; in qup_i2c_bam_xfer()
895 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
897 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
903 * already crossed the maximum length. Since the memory for all in qup_i2c_bam_xfer()
908 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
909 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
910 qup->is_last) { in qup_i2c_bam_xfer()
911 ret = qup_i2c_bam_schedule_desc(qup); in qup_i2c_bam_xfer()
915 qup_i2c_bam_clear_tag_buffers(qup); in qup_i2c_bam_xfer()
920 disable_irq(qup->irq); in qup_i2c_bam_xfer()
922 qup->msg = NULL; in qup_i2c_bam_xfer()
926 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, in qup_i2c_wait_for_complete() argument
932 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
934 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
935 ret = -ETIMEDOUT; in qup_i2c_wait_for_complete()
938 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
939 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
944 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) in qup_i2c_read_rx_fifo_v1() argument
946 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
947 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
951 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
954 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
955 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
957 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
960 blk->fifo_available--; in qup_i2c_read_rx_fifo_v1()
963 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
964 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v1()
967 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) in qup_i2c_write_rx_tags_v1() argument
969 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
975 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; in qup_i2c_write_rx_tags_v1()
978 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
981 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) in qup_i2c_conf_v1() argument
983 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
987 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
988 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
990 if (blk->is_tx_blk_mode) { in qup_i2c_conf_v1()
992 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
993 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
995 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
996 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
999 if (blk->total_rx_len) { in qup_i2c_conf_v1()
1000 if (blk->is_rx_blk_mode) { in qup_i2c_conf_v1()
1002 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1003 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1005 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1006 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1012 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
1013 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
1018 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v1()
1019 blk->fifo_available = 0; in qup_i2c_clear_blk_v1()
1020 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v1()
1023 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) in qup_i2c_conf_xfer_v1() argument
1025 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1029 qup_i2c_conf_v1(qup); in qup_i2c_conf_xfer_v1()
1030 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v1()
1034 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1036 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v1()
1040 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1041 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1042 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v1()
1043 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1046 qup_i2c_write_rx_tags_v1(qup); in qup_i2c_conf_xfer_v1()
1048 qup_i2c_write_tx_fifo_v1(qup); in qup_i2c_conf_xfer_v1()
1051 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v1()
1055 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1059 ret = qup_i2c_bus_active(qup, ONE_BYTE); in qup_i2c_conf_xfer_v1()
1062 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1066 static int qup_i2c_write_one(struct qup_i2c_dev *qup) in qup_i2c_write_one() argument
1068 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1069 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1071 qup->pos = 0; in qup_i2c_write_one()
1072 blk->total_tx_len = msg->len + 1; in qup_i2c_write_one()
1073 blk->total_rx_len = 0; in qup_i2c_write_one()
1075 return qup_i2c_conf_xfer_v1(qup, false); in qup_i2c_write_one()
1078 static int qup_i2c_read_one(struct qup_i2c_dev *qup) in qup_i2c_read_one() argument
1080 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1082 qup->pos = 0; in qup_i2c_read_one()
1083 blk->total_tx_len = 2; in qup_i2c_read_one()
1084 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1086 return qup_i2c_conf_xfer_v1(qup, true); in qup_i2c_read_one()
1093 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_xfer() local
1096 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1100 qup->bus_err = 0; in qup_i2c_xfer()
1101 qup->qup_err = 0; in qup_i2c_xfer()
1103 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1104 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); in qup_i2c_xfer()
1108 /* Configure QUP as I2C mini core */ in qup_i2c_xfer()
1109 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1112 if (qup_i2c_poll_state_i2c_master(qup)) { in qup_i2c_xfer()
1113 ret = -EIO; in qup_i2c_xfer()
1118 ret = -EINVAL; in qup_i2c_xfer()
1122 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1124 ret = qup_i2c_read_one(qup); in qup_i2c_xfer()
1126 ret = qup_i2c_write_one(qup); in qup_i2c_xfer()
1131 ret = qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_xfer()
1140 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer()
1141 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1150 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) in qup_i2c_conf_count_v2() argument
1152 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1155 if (blk->is_tx_blk_mode) in qup_i2c_conf_count_v2()
1156 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1157 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1159 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1160 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1162 if (blk->total_rx_len) { in qup_i2c_conf_count_v2()
1163 if (blk->is_rx_blk_mode) in qup_i2c_conf_count_v2()
1164 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1165 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1167 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1168 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1173 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1179 * QUP RESET state.
1181 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) in qup_i2c_conf_mode_v2() argument
1183 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1186 if (blk->is_tx_blk_mode) { in qup_i2c_conf_mode_v2()
1188 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1190 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1193 if (blk->is_rx_blk_mode) { in qup_i2c_conf_mode_v2()
1195 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1197 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1200 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1203 /* Clear required variables before starting of any QUP v2 sub transfer. */
1206 blk->send_last_word = false; in qup_i2c_clear_blk_v2()
1207 blk->tx_tags_sent = false; in qup_i2c_clear_blk_v2()
1208 blk->tx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1209 blk->tx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1210 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v2()
1212 blk->rx_tags_fetched = false; in qup_i2c_clear_blk_v2()
1213 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v2()
1214 blk->rx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1215 blk->rx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1216 blk->fifo_available = 0; in qup_i2c_clear_blk_v2()
1219 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1220 static void qup_i2c_recv_data(struct qup_i2c_dev *qup) in qup_i2c_recv_data() argument
1222 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1225 for (j = blk->rx_fifo_data_pos; in qup_i2c_recv_data()
1226 blk->cur_blk_len && blk->fifo_available; in qup_i2c_recv_data()
1227 blk->cur_blk_len--, blk->fifo_available--) { in qup_i2c_recv_data()
1229 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1231 *(blk->cur_data++) = blk->rx_fifo_data; in qup_i2c_recv_data()
1232 blk->rx_fifo_data >>= 8; in qup_i2c_recv_data()
1240 blk->rx_fifo_data_pos = j; in qup_i2c_recv_data()
1243 /* Receive tags for read message in QUP v2 i2c transfer. */
1244 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) in qup_i2c_recv_tags() argument
1246 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1248 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1249 blk->rx_fifo_data >>= blk->rx_tag_len * 8; in qup_i2c_recv_tags()
1250 blk->rx_fifo_data_pos = blk->rx_tag_len; in qup_i2c_recv_tags()
1251 blk->fifo_available -= blk->rx_tag_len; in qup_i2c_recv_tags()
1257 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1262 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) in qup_i2c_read_rx_fifo_v2() argument
1264 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1266 if (!blk->rx_tags_fetched) { in qup_i2c_read_rx_fifo_v2()
1267 qup_i2c_recv_tags(qup); in qup_i2c_read_rx_fifo_v2()
1268 blk->rx_tags_fetched = true; in qup_i2c_read_rx_fifo_v2()
1271 qup_i2c_recv_data(qup); in qup_i2c_read_rx_fifo_v2()
1272 if (!blk->cur_blk_len) in qup_i2c_read_rx_fifo_v2()
1273 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v2()
1277 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1282 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) in qup_i2c_write_blk_data() argument
1284 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1287 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; in qup_i2c_write_blk_data()
1288 (*len)--, blk->tx_fifo_free--) { in qup_i2c_write_blk_data()
1289 blk->tx_fifo_data |= *(*data)++ << (j * 8); in qup_i2c_write_blk_data()
1291 writel(blk->tx_fifo_data, in qup_i2c_write_blk_data()
1292 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1293 blk->tx_fifo_data = 0x0; in qup_i2c_write_blk_data()
1300 blk->tx_fifo_data_pos = j; in qup_i2c_write_blk_data()
1303 /* Transfer tags for read message in QUP v2 i2c transfer. */
1304 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) in qup_i2c_write_rx_tags_v2() argument
1306 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1308 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1309 if (blk->tx_fifo_data_pos) in qup_i2c_write_rx_tags_v2()
1310 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1315 * need to be written and QUP write tags can have maximum 256 data length, so
1317 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1335 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) in qup_i2c_write_tx_fifo_v2() argument
1337 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1339 if (!blk->tx_tags_sent) { in qup_i2c_write_tx_fifo_v2()
1340 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1341 &blk->tx_tag_len); in qup_i2c_write_tx_fifo_v2()
1342 blk->tx_tags_sent = true; in qup_i2c_write_tx_fifo_v2()
1345 if (blk->send_last_word) in qup_i2c_write_tx_fifo_v2()
1348 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1349 if (!blk->cur_blk_len) { in qup_i2c_write_tx_fifo_v2()
1350 if (!blk->tx_fifo_data_pos) in qup_i2c_write_tx_fifo_v2()
1353 if (blk->tx_fifo_free) in qup_i2c_write_tx_fifo_v2()
1356 blk->send_last_word = true; in qup_i2c_write_tx_fifo_v2()
1362 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1367 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1371 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, in qup_i2c_conf_xfer_v2() argument
1374 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1375 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1380 * done into 2 QUP reads. One with message length 1 while other one is in qup_i2c_conf_xfer_v2()
1384 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1390 blk->cur_data += 1; in qup_i2c_conf_xfer_v2()
1397 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1400 qup_i2c_conf_count_v2(qup); in qup_i2c_conf_xfer_v2()
1404 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v2()
1408 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1410 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v2()
1415 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1416 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1421 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v2()
1422 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1425 qup_i2c_write_rx_tags_v2(qup); in qup_i2c_conf_xfer_v2()
1427 qup_i2c_write_tx_fifo_v2(qup); in qup_i2c_conf_xfer_v2()
1430 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v2()
1434 ret = qup_i2c_wait_for_complete(qup, msg); in qup_i2c_conf_xfer_v2()
1440 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v2()
1446 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1453 * QUP block individually.
1455 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) in qup_i2c_xfer_v2_msg() argument
1459 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1460 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1461 u8 *msg_buf = msg->buf; in qup_i2c_xfer_v2_msg()
1463 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1464 qup_i2c_set_blk_data(qup, msg); in qup_i2c_xfer_v2_msg()
1466 for (i = 0; i < blk->count; i++) { in qup_i2c_xfer_v2_msg()
1467 data_len = qup_i2c_get_data_len(qup); in qup_i2c_xfer_v2_msg()
1468 blk->pos = i; in qup_i2c_xfer_v2_msg()
1469 blk->cur_tx_tags = blk->tags; in qup_i2c_xfer_v2_msg()
1470 blk->cur_blk_len = data_len; in qup_i2c_xfer_v2_msg()
1471 blk->tx_tag_len = in qup_i2c_xfer_v2_msg()
1472 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1474 blk->cur_data = msg_buf; in qup_i2c_xfer_v2_msg()
1477 blk->total_tx_len = blk->tx_tag_len; in qup_i2c_xfer_v2_msg()
1478 blk->rx_tag_len = 2; in qup_i2c_xfer_v2_msg()
1479 blk->total_rx_len = blk->rx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1481 blk->total_tx_len = blk->tx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1482 blk->total_rx_len = 0; in qup_i2c_xfer_v2_msg()
1485 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i, in qup_i2c_xfer_v2_msg()
1486 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1491 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && in qup_i2c_xfer_v2_msg()
1492 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1493 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) in qup_i2c_xfer_v2_msg()
1494 return -EPROTO; in qup_i2c_xfer_v2_msg()
1496 msg->len = msg->buf[0]; in qup_i2c_xfer_v2_msg()
1497 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1498 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true); in qup_i2c_xfer_v2_msg()
1499 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1503 msg->len += 1; in qup_i2c_xfer_v2_msg()
1507 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1514 * QUP v2 supports 3 modes
1530 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, in qup_i2c_determine_mode_v2() argument
1552 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1553 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1554 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1556 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1558 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1569 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_xfer_v2() local
1572 qup->bus_err = 0; in qup_i2c_xfer_v2()
1573 qup->qup_err = 0; in qup_i2c_xfer_v2()
1575 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1579 ret = qup_i2c_determine_mode_v2(qup, msgs, num); in qup_i2c_xfer_v2()
1583 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1584 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); in qup_i2c_xfer_v2()
1588 /* Configure QUP as I2C mini core */ in qup_i2c_xfer_v2()
1589 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1590 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1592 if (qup_i2c_poll_state_i2c_master(qup)) { in qup_i2c_xfer_v2()
1593 ret = -EIO; in qup_i2c_xfer_v2()
1597 if (qup->use_dma) { in qup_i2c_xfer_v2()
1598 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1600 qup->use_dma = false; in qup_i2c_xfer_v2()
1602 qup_i2c_conf_mode_v2(qup); in qup_i2c_xfer_v2()
1605 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1606 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1608 ret = qup_i2c_xfer_v2_msg(qup, idx, in qup_i2c_xfer_v2()
1613 qup->msg = NULL; in qup_i2c_xfer_v2()
1617 ret = qup_i2c_bus_active(qup, ONE_BYTE); in qup_i2c_xfer_v2()
1620 qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_xfer_v2()
1625 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer_v2()
1626 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1647 * The QUP block will issue a NACK and STOP on the bus when reaching
1660 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) in qup_i2c_enable_clocks() argument
1662 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1663 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1666 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) in qup_i2c_disable_clocks() argument
1670 qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_disable_clocks()
1671 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1672 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1674 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1675 qup_i2c_vote_bw(qup, 0); in qup_i2c_disable_clocks()
1676 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1688 struct qup_i2c_dev *qup; in qup_i2c_probe() local
1697 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1698 if (!qup) in qup_i2c_probe()
1699 return -ENOMEM; in qup_i2c_probe()
1701 qup->dev = &pdev->dev; in qup_i2c_probe()
1702 init_completion(&qup->xfer); in qup_i2c_probe()
1703 platform_set_drvdata(pdev, qup); in qup_i2c_probe()
1706 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1709 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1711 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1716 if (device_is_compatible(&pdev->dev, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1717 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1718 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1721 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1722 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1724 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1727 ret = qup_i2c_req_dma(qup); in qup_i2c_probe()
1729 if (ret == -EPROBE_DEFER) in qup_i2c_probe()
1734 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1736 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1737 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1739 if (!qup->btx.sg) { in qup_i2c_probe()
1740 ret = -ENOMEM; in qup_i2c_probe()
1743 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1745 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1746 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1748 if (!qup->brx.sg) { in qup_i2c_probe()
1749 ret = -ENOMEM; in qup_i2c_probe()
1752 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1757 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1759 if (!qup->start_tag.start) { in qup_i2c_probe()
1760 ret = -ENOMEM; in qup_i2c_probe()
1764 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1765 if (!qup->brx.tag.start) { in qup_i2c_probe()
1766 ret = -ENOMEM; in qup_i2c_probe()
1770 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1771 if (!qup->btx.tag.start) { in qup_i2c_probe()
1772 ret = -ENOMEM; in qup_i2c_probe()
1775 qup->is_dma = true; in qup_i2c_probe()
1777 qup->icc_path = devm_of_icc_get(&pdev->dev, NULL); in qup_i2c_probe()
1778 if (IS_ERR(qup->icc_path)) in qup_i2c_probe()
1779 return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path), in qup_i2c_probe()
1786 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1788 ret = -EINVAL; in qup_i2c_probe()
1792 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1793 if (IS_ERR(qup->base)) { in qup_i2c_probe()
1794 ret = PTR_ERR(qup->base); in qup_i2c_probe()
1798 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1799 if (qup->irq < 0) { in qup_i2c_probe()
1800 ret = qup->irq; in qup_i2c_probe()
1804 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1805 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1806 "src-clock-hz", &src_clk_freq); in qup_i2c_probe()
1808 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1811 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1813 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1814 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1815 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1816 ret = PTR_ERR(qup->clk); in qup_i2c_probe()
1820 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1821 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1822 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1823 ret = PTR_ERR(qup->pclk); in qup_i2c_probe()
1826 qup_i2c_enable_clocks(qup); in qup_i2c_probe()
1827 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1829 qup->src_clk_freq = src_clk_freq; in qup_i2c_probe()
1832 * Bootloaders might leave a pending interrupt on certain QUP's, in qup_i2c_probe()
1835 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1836 ret = qup_i2c_poll_state_valid(qup); in qup_i2c_probe()
1840 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1842 "i2c_qup", qup); in qup_i2c_probe()
1844 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1848 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1849 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1851 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1859 ret = -EIO; in qup_i2c_probe()
1862 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1866 ret = -EIO; in qup_i2c_probe()
1869 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1873 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a in qup_i2c_probe()
1877 qup->in_blk_sz /= 2; in qup_i2c_probe()
1878 qup->out_blk_sz /= 2; in qup_i2c_probe()
1879 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1880 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1881 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1883 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1884 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1885 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1889 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1892 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1896 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; in qup_i2c_probe()
1897 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1900 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; in qup_i2c_probe()
1901 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1909 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1910 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1911 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1913 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1914 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1915 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1917 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1918 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1919 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1920 qup->is_last = true; in qup_i2c_probe()
1922 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1924 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1925 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1926 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1927 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1929 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1936 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1937 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1939 qup_i2c_disable_clocks(qup); in qup_i2c_probe()
1941 if (qup->btx.dma) in qup_i2c_probe()
1942 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1943 if (qup->brx.dma) in qup_i2c_probe()
1944 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1950 struct qup_i2c_dev *qup = platform_get_drvdata(pdev); in qup_i2c_remove() local
1952 if (qup->is_dma) { in qup_i2c_remove()
1953 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1954 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1957 disable_irq(qup->irq); in qup_i2c_remove()
1958 qup_i2c_disable_clocks(qup); in qup_i2c_remove()
1959 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1960 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1961 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
1966 struct qup_i2c_dev *qup = dev_get_drvdata(device); in qup_i2c_pm_suspend_runtime() local
1969 qup_i2c_disable_clocks(qup); in qup_i2c_pm_suspend_runtime()
1975 struct qup_i2c_dev *qup = dev_get_drvdata(device); in qup_i2c_pm_resume_runtime() local
1978 qup_i2c_enable_clocks(qup); in qup_i2c_pm_resume_runtime()
2004 { .compatible = "qcom,i2c-qup-v1.1.1" },
2005 { .compatible = "qcom,i2c-qup-v2.1.1" },
2006 { .compatible = "qcom,i2c-qup-v2.2.1" },
2024 MODULE_DESCRIPTION("Qualcomm QUP based I2C controller");