1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/i2c.h>
8 #include <linux/i2c-smbus.h>
13 /* Controller command patterns */
22 /* Controller opcode word (bits 60:57) */
31 /* Controller extended opcode word (bits 34:32) */
39 /* Controller command and status bits */
40 #define TWSI_CTL_CE		0x80	/* High level controller enable */
42 #define TWSI_CTL_STA		0x20	/* Controller-mode start, HW clears when done */
43 #define TWSI_CTL_STP		0x10	/* Controller-mode stop, HW clears when done */
101 #define OCTEON_REG_SW_TWSI(x)		((x)->roff.sw_twsi)
102 #define OCTEON_REG_TWSI_INT(x)		((x)->roff.twsi_int)
103 #define OCTEON_REG_SW_TWSI_EXT(x)	((x)->roff.sw_twsi_ext)
104 #define OCTEON_REG_MODE(x)		((x)->roff.mode)
145  * octeon_i2c_reg_write - write an I2C core register
146  * @i2c: The struct octeon_i2c
150  * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
152 static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)  in octeon_i2c_reg_write()  argument
157 	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_write()
159 		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_write()
160 		if (--tries < 0)  in octeon_i2c_reg_write()
165 #define octeon_i2c_ctl_write(i2c, val)					\  argument
166 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
167 #define octeon_i2c_data_write(i2c, val)					\  argument
168 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
171  * octeon_i2c_reg_read - read lower bits of an I2C core register
172  * @i2c: The struct octeon_i2c
177  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
179 static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,  in octeon_i2c_reg_read()  argument
185 	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_read()
187 		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_reg_read()
188 		if (--tries < 0) {  in octeon_i2c_reg_read()
191 				*error = -EIO;  in octeon_i2c_reg_read()
199 #define octeon_i2c_ctl_read(i2c)					\  argument
200 	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
201 #define octeon_i2c_data_read(i2c, error)				\  argument
202 	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
203 #define octeon_i2c_stat_read(i2c)					\  argument
204 	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
207  * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
208  * @i2c: The struct octeon_i2c
212 static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)  in octeon_i2c_read_int()  argument
214 	return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));  in octeon_i2c_read_int()
218  * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
219  * @i2c: The struct octeon_i2c
222 static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)  in octeon_i2c_write_int()  argument
224 	octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));  in octeon_i2c_write_int()
231  * octeon_i2c_is_otx2 - check for chip ID
238 	u32 chip_id = FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device);  in octeon_i2c_is_otx2()
246 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
247 void octeon_i2c_set_clock(struct octeon_i2c *i2c);