124 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */  macro
745 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
747 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
933 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_reset()
1323 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1348 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1395 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1403 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {  in npcm_i2c_int_slave_handler()
1412 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1686 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1688 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1737 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_nack()
1857 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1862 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1866 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1983 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
1986 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
2276 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()
2279 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()