99 #define NPCM_I2CCTL1			0x06  macro
706 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
712 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
772 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
778 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
785 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
788 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
801 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
804 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
823 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
829 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
836 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
839 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
857 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
863 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
875 		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
880 		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
916 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
923 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
1920 		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&  in npcm_i2c_int_master_handler()
2169 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()
2171 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()