Lines Matching +full:i2c +full:- +full:arbitrator
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
85 #define I2C_DRV_NAME "i2c-mt65xx"
88 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
90 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
91 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
92 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
93 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
287 struct i2c_adapter adap; /* i2c host adapter */
292 /* set in i2c probe */
293 void __iomem *base; /* i2c base addr */
295 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
296 bool have_pmic; /* can use i2c pins from PMIC */
297 bool use_push_pull; /* IO config push-pull mode */
315 * @min_su_sta_ns: min set-up time for a repeated START condition
317 * @min_su_dat_ns: min data set-up time
329 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
336 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
343 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
525 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
526 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
527 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
528 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
529 { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
530 { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
531 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
532 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
533 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
534 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
535 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
536 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
541 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) in mtk_i2c_readw() argument
543 return readw(i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_readw()
546 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, in mtk_i2c_writew() argument
549 writew(val, i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_writew()
552 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) in mtk_i2c_init_hw() argument
558 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); in mtk_i2c_init_hw()
559 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
560 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
562 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_init_hw()
563 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
565 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
568 i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
569 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, in mtk_i2c_init_hw()
572 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
573 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
575 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
577 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
578 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
582 if (i2c->use_push_pull) in mtk_i2c_init_hw()
583 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
585 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
587 if (i2c->dev_comp->dcm) in mtk_i2c_init_hw()
588 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); in mtk_i2c_init_hw()
590 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); in mtk_i2c_init_hw()
591 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); in mtk_i2c_init_hw()
592 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_init_hw()
593 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); in mtk_i2c_init_hw()
595 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) in mtk_i2c_init_hw()
600 if (i2c->dev_comp->timing_adjust) { in mtk_i2c_init_hw()
601 ext_conf_val = i2c->ac_timing.ext; in mtk_i2c_init_hw()
602 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, in mtk_i2c_init_hw()
604 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, in mtk_i2c_init_hw()
606 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, in mtk_i2c_init_hw()
609 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_init_hw()
610 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, in mtk_i2c_init_hw()
612 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); in mtk_i2c_init_hw()
613 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, in mtk_i2c_init_hw()
616 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, in mtk_i2c_init_hw()
618 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, in mtk_i2c_init_hw()
620 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, in mtk_i2c_init_hw()
622 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, in mtk_i2c_init_hw()
626 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); in mtk_i2c_init_hw()
628 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ in mtk_i2c_init_hw()
629 if (i2c->have_pmic) in mtk_i2c_init_hw()
630 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); in mtk_i2c_init_hw()
634 if (i2c->dev_comp->dma_sync) in mtk_i2c_init_hw()
637 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw()
638 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); in mtk_i2c_init_hw()
659 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, in mtk_i2c_get_clk_div_restri() argument
664 if (i2c->dev_comp->ltiming_adjust == 0) in mtk_i2c_get_clk_div_restri()
668 if (i2c->ac_timing.inter_clk_div == 0) in mtk_i2c_get_clk_div_restri()
673 if (i2c->ac_timing.inter_clk_div == 0) in mtk_i2c_get_clk_div_restri()
674 clk_div_restri = -1; in mtk_i2c_get_clk_div_restri()
675 else if (i2c->ac_timing.inter_clk_div == 1) in mtk_i2c_get_clk_div_restri()
685 * Check and Calculate i2c ac-timing
689 * xxx_cnt_div = spec->min_xxx_ns / sample_ns
696 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, in mtk_i2c_check_ac_timing() argument
708 if (!i2c->dev_comp->timing_adjust) in mtk_i2c_check_ac_timing()
711 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
716 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
721 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + in mtk_i2c_check_ac_timing()
722 i2c->timing_info.scl_int_delay_ns, clk_ns); in mtk_i2c_check_ac_timing()
724 return -1; in mtk_i2c_check_ac_timing()
726 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); in mtk_i2c_check_ac_timing()
730 high_cnt = 2 * step_cnt - low_cnt; in mtk_i2c_check_ac_timing()
736 return -2; in mtk_i2c_check_ac_timing()
739 sda_max = spec->max_hd_dat_ns / sample_ns; in mtk_i2c_check_ac_timing()
743 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); in mtk_i2c_check_ac_timing()
748 return -3; in mtk_i2c_check_ac_timing()
751 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
752 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_check_ac_timing()
754 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); in mtk_i2c_check_ac_timing()
755 i2c->ac_timing.ltiming |= (sample_cnt << 12) | in mtk_i2c_check_ac_timing()
757 i2c->ac_timing.ext &= ~GENMASK(7, 1); in mtk_i2c_check_ac_timing()
758 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); in mtk_i2c_check_ac_timing()
760 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
762 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
765 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); in mtk_i2c_check_ac_timing()
766 i2c->ac_timing.sda_timing |= (1 << 12) | in mtk_i2c_check_ac_timing()
769 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
770 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); in mtk_i2c_check_ac_timing()
771 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); in mtk_i2c_check_ac_timing()
772 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); in mtk_i2c_check_ac_timing()
774 i2c->ac_timing.scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
776 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
780 i2c->ac_timing.sda_timing = (1 << 12) | in mtk_i2c_check_ac_timing()
788 * Calculate i2c port speed
795 * less than or equal to i2c->speed_hz. The calculation try to get
798 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, in mtk_i2c_calculate_speed() argument
811 int ret = -EINVAL; in mtk_i2c_calculate_speed()
830 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); in mtk_i2c_calculate_speed()
837 ret = mtk_i2c_check_ac_timing(i2c, clk_src, in mtk_i2c_calculate_speed()
838 target_speed, step_cnt - 1, sample_cnt - 1); in mtk_i2c_calculate_speed()
851 return -EINVAL; in mtk_i2c_calculate_speed()
856 if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > in mtk_i2c_calculate_speed()
861 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); in mtk_i2c_calculate_speed()
862 return -EINVAL; in mtk_i2c_calculate_speed()
865 *timing_step_cnt = step_cnt - 1; in mtk_i2c_calculate_speed()
866 *timing_sample_cnt = sample_cnt - 1; in mtk_i2c_calculate_speed()
871 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) in mtk_i2c_set_speed() argument
883 target_speed = i2c->speed_hz; in mtk_i2c_set_speed()
884 parent_clk /= i2c->clk_src_div; in mtk_i2c_set_speed()
886 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
888 else if (i2c->dev_comp->timing_adjust) in mtk_i2c_set_speed()
895 i2c->ac_timing.inter_clk_div = clk_div - 1; in mtk_i2c_set_speed()
899 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
906 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
909 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
915 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_set_speed()
918 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
919 i2c->ltiming_reg = in mtk_i2c_set_speed()
923 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
929 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
932 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; in mtk_i2c_set_speed()
934 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
935 i2c->ltiming_reg = in mtk_i2c_set_speed()
946 static void i2c_dump_register(struct mtk_i2c *i2c) in i2c_dump_register() argument
948 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", in i2c_dump_register()
949 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), in i2c_dump_register()
950 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); in i2c_dump_register()
951 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", in i2c_dump_register()
952 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), in i2c_dump_register()
953 mtk_i2c_readw(i2c, OFFSET_CONTROL)); in i2c_dump_register()
954 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", in i2c_dump_register()
955 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), in i2c_dump_register()
956 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); in i2c_dump_register()
957 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", in i2c_dump_register()
958 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), in i2c_dump_register()
959 mtk_i2c_readw(i2c, OFFSET_TIMING)); in i2c_dump_register()
960 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", in i2c_dump_register()
961 mtk_i2c_readw(i2c, OFFSET_START), in i2c_dump_register()
962 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); in i2c_dump_register()
963 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", in i2c_dump_register()
964 mtk_i2c_readw(i2c, OFFSET_HS), in i2c_dump_register()
965 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); in i2c_dump_register()
966 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", in i2c_dump_register()
967 mtk_i2c_readw(i2c, OFFSET_DCM_EN), in i2c_dump_register()
968 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); in i2c_dump_register()
969 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", in i2c_dump_register()
970 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), in i2c_dump_register()
971 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); in i2c_dump_register()
972 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", in i2c_dump_register()
973 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), in i2c_dump_register()
974 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); in i2c_dump_register()
975 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { in i2c_dump_register()
976 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", in i2c_dump_register()
977 mtk_i2c_readw(i2c, OFFSET_LTIMING), in i2c_dump_register()
978 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); in i2c_dump_register()
980 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", in i2c_dump_register()
981 readl(i2c->pdmabase + OFFSET_INT_FLAG), in i2c_dump_register()
982 readl(i2c->pdmabase + OFFSET_INT_EN)); in i2c_dump_register()
983 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", in i2c_dump_register()
984 readl(i2c->pdmabase + OFFSET_EN), in i2c_dump_register()
985 readl(i2c->pdmabase + OFFSET_CON)); in i2c_dump_register()
986 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", in i2c_dump_register()
987 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), in i2c_dump_register()
988 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); in i2c_dump_register()
989 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", in i2c_dump_register()
990 readl(i2c->pdmabase + OFFSET_TX_LEN), in i2c_dump_register()
991 readl(i2c->pdmabase + OFFSET_RX_LEN)); in i2c_dump_register()
992 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", in i2c_dump_register()
993 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), in i2c_dump_register()
994 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); in i2c_dump_register()
997 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, in mtk_i2c_do_transfer() argument
1013 i2c->irq_stat = 0; in mtk_i2c_do_transfer()
1015 if (i2c->auto_restart) in mtk_i2c_do_transfer()
1018 reinit_completion(&i2c->msg_complete); in mtk_i2c_do_transfer()
1020 if (i2c->dev_comp->apdma_sync && in mtk_i2c_do_transfer()
1021 i2c->op != I2C_MASTER_WRRD && num > 1) { in mtk_i2c_do_transfer()
1022 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); in mtk_i2c_do_transfer()
1024 i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
1026 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, in mtk_i2c_do_transfer()
1031 dev_err(i2c->dev, "DMA warm reset timeout\n"); in mtk_i2c_do_transfer()
1032 return -ETIMEDOUT; in mtk_i2c_do_transfer()
1035 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
1036 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
1037 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
1038 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, in mtk_i2c_do_transfer()
1042 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer()
1044 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) in mtk_i2c_do_transfer()
1047 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
1050 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()
1053 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); in mtk_i2c_do_transfer()
1056 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1059 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); in mtk_i2c_do_transfer()
1062 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1066 if (i2c->op == I2C_MASTER_WRRD) { in mtk_i2c_do_transfer()
1067 if (i2c->dev_comp->aux_len_reg) { in mtk_i2c_do_transfer()
1068 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
1069 mtk_i2c_writew(i2c, (msgs + 1)->len, in mtk_i2c_do_transfer()
1072 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, in mtk_i2c_do_transfer()
1075 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
1077 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
1078 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
1081 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_do_transfer()
1083 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
1088 if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1089 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1090 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1094 return -ENOMEM; in mtk_i2c_do_transfer()
1096 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1097 msgs->len, DMA_FROM_DEVICE); in mtk_i2c_do_transfer()
1098 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1101 return -ENOMEM; in mtk_i2c_do_transfer()
1104 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1106 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1109 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1110 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1111 } else if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1112 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1113 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1117 return -ENOMEM; in mtk_i2c_do_transfer()
1119 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1120 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1121 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1124 return -ENOMEM; in mtk_i2c_do_transfer()
1127 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1129 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1132 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1133 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1135 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1136 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1140 return -ENOMEM; in mtk_i2c_do_transfer()
1142 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1143 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1144 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1147 return -ENOMEM; in mtk_i2c_do_transfer()
1152 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1153 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1157 return -ENOMEM; in mtk_i2c_do_transfer()
1160 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1161 (msgs + 1)->len, in mtk_i2c_do_transfer()
1163 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1164 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1165 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1170 return -ENOMEM; in mtk_i2c_do_transfer()
1173 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1175 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1178 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1181 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1182 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1183 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1184 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1187 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); in mtk_i2c_do_transfer()
1189 if (!i2c->auto_restart) { in mtk_i2c_do_transfer()
1196 mtk_i2c_writew(i2c, start_reg, OFFSET_START); in mtk_i2c_do_transfer()
1198 ret = wait_for_completion_timeout(&i2c->msg_complete, in mtk_i2c_do_transfer()
1199 i2c->adap.timeout); in mtk_i2c_do_transfer()
1202 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1205 if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1206 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1207 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1210 } else if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1211 dma_unmap_single(i2c->dev, rpaddr, in mtk_i2c_do_transfer()
1212 msgs->len, DMA_FROM_DEVICE); in mtk_i2c_do_transfer()
1216 dma_unmap_single(i2c->dev, wpaddr, msgs->len, in mtk_i2c_do_transfer()
1218 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, in mtk_i2c_do_transfer()
1226 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); in mtk_i2c_do_transfer()
1227 i2c_dump_register(i2c); in mtk_i2c_do_transfer()
1228 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1229 return -ETIMEDOUT; in mtk_i2c_do_transfer()
1232 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { in mtk_i2c_do_transfer()
1233 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); in mtk_i2c_do_transfer()
1234 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1235 return -ENXIO; in mtk_i2c_do_transfer()
1246 struct mtk_i2c *i2c = i2c_get_adapdata(adap); in mtk_i2c_transfer() local
1248 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_transfer()
1252 i2c->auto_restart = i2c->dev_comp->auto_restart; in mtk_i2c_transfer()
1255 if (i2c->auto_restart && num == 2) { in mtk_i2c_transfer()
1258 i2c->auto_restart = 0; in mtk_i2c_transfer()
1262 if (i2c->auto_restart && num >= 2 && in mtk_i2c_transfer()
1263 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) in mtk_i2c_transfer()
1267 i2c->ignore_restart_irq = true; in mtk_i2c_transfer()
1269 i2c->ignore_restart_irq = false; in mtk_i2c_transfer()
1271 while (left_num--) { in mtk_i2c_transfer()
1272 if (!msgs->buf) { in mtk_i2c_transfer()
1273 dev_dbg(i2c->dev, "data buffer is NULL.\n"); in mtk_i2c_transfer()
1274 ret = -EINVAL; in mtk_i2c_transfer()
1278 if (msgs->flags & I2C_M_RD) in mtk_i2c_transfer()
1279 i2c->op = I2C_MASTER_RD; in mtk_i2c_transfer()
1281 i2c->op = I2C_MASTER_WR; in mtk_i2c_transfer()
1283 if (!i2c->auto_restart) { in mtk_i2c_transfer()
1286 i2c->op = I2C_MASTER_WRRD; in mtk_i2c_transfer()
1287 left_num--; in mtk_i2c_transfer()
1292 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); in mtk_i2c_transfer()
1302 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_transfer()
1308 struct mtk_i2c *i2c = dev_id; in mtk_i2c_irq() local
1309 u16 restart_flag = i2c->auto_restart ? I2C_RS_TRANSFER : 0; in mtk_i2c_irq()
1312 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_irq()
1313 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); in mtk_i2c_irq()
1316 * when occurs ack error, i2c controller generate two interrupts in mtk_i2c_irq()
1318 * i2c->irq_stat need keep the two interrupt value. in mtk_i2c_irq()
1320 i2c->irq_stat |= intr_stat; in mtk_i2c_irq()
1322 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { in mtk_i2c_irq()
1323 i2c->ignore_restart_irq = false; in mtk_i2c_irq()
1324 i2c->irq_stat = 0; in mtk_i2c_irq()
1325 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | in mtk_i2c_irq()
1328 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) in mtk_i2c_irq()
1329 complete(&i2c->msg_complete); in mtk_i2c_irq()
1349 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) in mtk_i2c_parse_dt() argument
1353 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); in mtk_i2c_parse_dt()
1355 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; in mtk_i2c_parse_dt()
1357 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); in mtk_i2c_parse_dt()
1361 if (i2c->clk_src_div == 0) in mtk_i2c_parse_dt()
1362 return -EINVAL; in mtk_i2c_parse_dt()
1364 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); in mtk_i2c_parse_dt()
1365 i2c->use_push_pull = in mtk_i2c_parse_dt()
1366 of_property_read_bool(np, "mediatek,use-push-pull"); in mtk_i2c_parse_dt()
1368 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); in mtk_i2c_parse_dt()
1376 struct mtk_i2c *i2c; in mtk_i2c_probe() local
1379 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in mtk_i2c_probe()
1380 if (!i2c) in mtk_i2c_probe()
1381 return -ENOMEM; in mtk_i2c_probe()
1383 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in mtk_i2c_probe()
1384 if (IS_ERR(i2c->base)) in mtk_i2c_probe()
1385 return PTR_ERR(i2c->base); in mtk_i2c_probe()
1387 i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); in mtk_i2c_probe()
1388 if (IS_ERR(i2c->pdmabase)) in mtk_i2c_probe()
1389 return PTR_ERR(i2c->pdmabase); in mtk_i2c_probe()
1395 init_completion(&i2c->msg_complete); in mtk_i2c_probe()
1397 i2c->dev_comp = of_device_get_match_data(&pdev->dev); in mtk_i2c_probe()
1398 i2c->adap.dev.of_node = pdev->dev.of_node; in mtk_i2c_probe()
1399 i2c->dev = &pdev->dev; in mtk_i2c_probe()
1400 i2c->adap.dev.parent = &pdev->dev; in mtk_i2c_probe()
1401 i2c->adap.owner = THIS_MODULE; in mtk_i2c_probe()
1402 i2c->adap.algo = &mtk_i2c_algorithm; in mtk_i2c_probe()
1403 i2c->adap.quirks = i2c->dev_comp->quirks; in mtk_i2c_probe()
1404 i2c->adap.timeout = 2 * HZ; in mtk_i2c_probe()
1405 i2c->adap.retries = 1; in mtk_i2c_probe()
1406 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); in mtk_i2c_probe()
1407 if (IS_ERR(i2c->adap.bus_regulator)) { in mtk_i2c_probe()
1408 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) in mtk_i2c_probe()
1409 i2c->adap.bus_regulator = NULL; in mtk_i2c_probe()
1411 return PTR_ERR(i2c->adap.bus_regulator); in mtk_i2c_probe()
1414 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); in mtk_i2c_probe()
1416 return -EINVAL; in mtk_i2c_probe()
1418 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) in mtk_i2c_probe()
1419 return -EINVAL; in mtk_i2c_probe()
1421 /* Fill in clk-bulk IDs */ in mtk_i2c_probe()
1423 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; in mtk_i2c_probe()
1426 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); in mtk_i2c_probe()
1427 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { in mtk_i2c_probe()
1428 dev_err(&pdev->dev, "cannot get main clock\n"); in mtk_i2c_probe()
1429 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); in mtk_i2c_probe()
1432 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); in mtk_i2c_probe()
1433 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { in mtk_i2c_probe()
1434 dev_err(&pdev->dev, "cannot get dma clock\n"); in mtk_i2c_probe()
1435 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); in mtk_i2c_probe()
1438 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); in mtk_i2c_probe()
1439 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) in mtk_i2c_probe()
1440 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); in mtk_i2c_probe()
1442 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); in mtk_i2c_probe()
1443 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { in mtk_i2c_probe()
1444 dev_err(&pdev->dev, "cannot get pmic clock\n"); in mtk_i2c_probe()
1445 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); in mtk_i2c_probe()
1448 if (i2c->have_pmic) { in mtk_i2c_probe()
1449 if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { in mtk_i2c_probe()
1450 dev_err(&pdev->dev, "cannot get pmic clock\n"); in mtk_i2c_probe()
1451 return -ENODEV; in mtk_i2c_probe()
1458 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); in mtk_i2c_probe()
1460 ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); in mtk_i2c_probe()
1462 dev_err(&pdev->dev, "Failed to set the speed.\n"); in mtk_i2c_probe()
1463 return -EINVAL; in mtk_i2c_probe()
1466 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_probe()
1467 ret = dma_set_mask(&pdev->dev, in mtk_i2c_probe()
1468 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); in mtk_i2c_probe()
1470 dev_err(&pdev->dev, "dma_set_mask return error.\n"); in mtk_i2c_probe()
1475 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1477 dev_err(&pdev->dev, "clock enable failed!\n"); in mtk_i2c_probe()
1480 mtk_i2c_init_hw(i2c); in mtk_i2c_probe()
1481 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1483 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, in mtk_i2c_probe()
1485 dev_name(&pdev->dev), i2c); in mtk_i2c_probe()
1487 dev_err(&pdev->dev, in mtk_i2c_probe()
1488 "Request I2C IRQ %d fail\n", irq); in mtk_i2c_probe()
1492 i2c_set_adapdata(&i2c->adap, i2c); in mtk_i2c_probe()
1493 ret = i2c_add_adapter(&i2c->adap); in mtk_i2c_probe()
1497 platform_set_drvdata(pdev, i2c); in mtk_i2c_probe()
1502 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_probe()
1509 struct mtk_i2c *i2c = platform_get_drvdata(pdev); in mtk_i2c_remove() local
1511 i2c_del_adapter(&i2c->adap); in mtk_i2c_remove()
1513 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_remove()
1518 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_suspend_noirq() local
1520 i2c_mark_adapter_suspended(&i2c->adap); in mtk_i2c_suspend_noirq()
1521 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_suspend_noirq()
1529 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_resume_noirq() local
1531 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_resume_noirq()
1537 mtk_i2c_init_hw(i2c); in mtk_i2c_resume_noirq()
1539 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); in mtk_i2c_resume_noirq()
1541 i2c_mark_adapter_resumed(&i2c->adap); in mtk_i2c_resume_noirq()
1564 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");